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PDF RT9173C Data sheet ( Hoja de datos )
| Número de pieza | RT9173C | |
| Descripción | 2A Sink/Source Bus Termination Regulator | |
| Fabricantes | Richtek Technology Corporation | |
| Logotipo |  |
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RT9173C
Cost-Effective, 2A Sink/Source Bus Termination Regulator
General D escription
The RT9173C is a simple, cost-effective and high-speed
linear regulator designed to generate termination voltage
in double data rate (DDR) memory system to comply with
the JEDEC SSTL_2 a nd SSTL_18 or other spe cific
interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices
requirements. The regulator is capable of actively sinking
or sourcing up to 2Awhile regulating an output voltage to
within 40mV. The output termination voltage cab be tightly
regulated to track 1/2VDDQ by two external voltage divider
resistors or the dseired output voltage cnabe pro-grammed
by externally forcing the REFEN pin voltage.
The RT9173C also incorporates a high-speed differential
amplifier to provide ultra-fsat response in line/load transient.
Other features include extremely low initial offset voltage,
excellent load regulation, current limiting in bi-directions
and on-chip thermal shut-down protection.
The RT9173C are available in the SOP-8 (Exposed Pad)
surface mount packages.
Ordering Information
RT9173C
Package Type
SP : SOP-8 (Exposed Pad-Option 1)
Note :
Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
Richtek products are :
` RoHS compli ant and compatible with the current require-
ments of IPC/JEDEC J-ST D-020.
` Suitable for use in SnPb or Pb-free soldering processes.
Feature s
z Ideal for DDR-I, DDR-II and DDR-III VTT Applications
z Sink and Source 2A Continuous Current
z Integrated Power MOSFETs
z Generates Termination Voltage for SSTL_2,
SSTL _18, HSTL, SCSI-2 and SCSI-3 Interfaces
z High Accuracy Output Voltage at Full-Load
z Output Adjustment by Two External Resistors
z Low External Component Count
z Shutdown for Suspend to RAM (STR) Functionality
with High-Impedance Output
z Current Limiting Protection
z On-Chip Thermal Protection
z Available in SOP-8 (Exposed Pad) Packages
z VIN and VCNTL No Power Sequence Issue
z RoHS Compliant and 100% Lead (Pb)-Free
Application s
z Desktop PCs, Notebooks, and Workstations
z Graphics Card MemoryTermination
z Set Top Boxes, Digital TVs, Printers
z Embedded Systems
z Active Termination Buses
z DDR-I, DDR-II and DDR-III Memory Systems
Pin Configurations
(TOP VIEW)
VIN
GND
REFEN
VOUT
8
27
3
GND
9
6
45
NC
NC
VCNTL
NC
SOP-8 (Exposed Pad)
DS9173C-13 April 2011
www.richtek.com
1
http://www.Datasheet4U.com
1 page  
RT9173C
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at the se or a ny other condition s beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may re main possibility to af fect device reli ability.
Note 2. θJA is me asured in the n atural conve ction at TA = 25°C on a high ef fective thermal conductivity te st board (4 Layers,
2S2P) of JEDEC 51-7 thermal me asurement standard. The case point of θJC is on the expose pad for SOP-8 (Exposed
Pad) pa ckage.
Note 3. Devices are ESD sen sitive. Ha ndling pre caution re commended.
Note 4. The device is not guara nteed to function outside its operating condition s.
Note 5. VOS offset is the voltage me asurement defined as VOUT subtracted from VREFEN.
Note 6. Regulation is me asured at con stant junction te mperature by using a 5ms current pulse. Devices are te sted f or loa d
regulation in the loa d range from 0A to 2A.
Note 7. Standby current is the in put current drawn by a regulator when the output voltage is disa bled by a shutdown sign al on
REFEN pin (VIL < 0.2V). It is measured with VIN = VCNTL = 5V.
DS9173C-13 April 2011
www.richtek.com
5
5 Page 
RT9173C
RDS(ON) vs. Temperature
0.40
VCNTL = 5V
0.35
0.30
0.25
0.20
0.15
0.10
-50
-25
0 25 50 75
Temperature (°C)
Figure 5
100 125
on standard JEDEC 51-7 (4 layers, 2S2P) thermal test
board. The maximum power dissipation at TA = 25°C can
be calculated by following formula:
PD(MAX) = (125°C - 25°C) / 75°C/W = 1.33W
Figure 6 show the package sectional drawing of SOP-8
(Exposed Pa d). Every pa ckage ha s several thermal
dissipation paths. As show in Figure 7, the thermal
resistance equivalent circuit of SOP-8 (Exposed Pd)a. The
path 2 is the main path due to these materials thermal
conductivity. We define the exposed pad is the case point
of the path 2.
Ambient
Molding Compound
Gold Line
Lead Frame
Input Capacitor and Layout Consideration
Die Pad
Place the input bypass capacitor as close as possible to
the RT9173C. A low ESR capacitor larger than 470uF is
recommended for the input capacitor. Use short and wide
traces to mini mize parasitic resistance and inductance.
Inappropriate layout may result in large pasriatic inductance
and cause undesired oscillation between RT9173C and
the preceding power converte.r
Case (Exposed Pad)
Figure 6. SOP-8 (Exposed Pad) Package Sectional
Drawing
RGOLD-LINE RLEAD FRAME RPCB
Thermal Consideration
path 1
RT9173C regulators have internal thermal limiting circuitry
designed to protect the device during overload conditions. Junction
For continued operation, do not exceed maximum operation
junction temperature 125 °C. The power dissipation
definition in device is:
RDIE RDIE-ATTACH RDIE-PAD
RPCB
path 2
Case
(Exposed Pad)
RMOLDING-COMPOUND
Ambient
PD = (VIN - VOUT) x IOUT + VIN x IQ
The maximum power dissipation depends on the thermal
resista nce of IC pa ckage, PCB layout, the rate of
surroundings airflow and temperature diference between
junction to ambient. The maximum power dissipation can
be calculated by following formula:
PD(MAX) = (TJ(MAX) -TA ) /θJA
Where T J(MAX) is the maximum operation junction
temperature 125°C, TA is the ambient temperature and the
θJA is the junction to a mbient thermal re sistance. The
junction to a mbient thermal re sistance ( θJA is layout
dependent) for SOP-8 package (Exposed Pad) is 75°C/W
path 3
Figure 7. Thermal Resistance Equivalent Circuit
The thermal resistance θJA of SOP-8 (Exposed Pa d) is
determined by the package design and the PCB design.
However, the package design has been decided. If possible,
it's useful to increase thermal performance by the PCB
design. The thermal re sistance ca n be de creased by
adding copper under the expose pad of SOP-8 package.
About PCB layout, the Figure 8 show the relation between
thermal resistance θJA and copper are a on a sta ndard
JEDEC 51-7 (4 layers, 2S2P) thermal test board at
TA = 25°C.We have to consider the copper couldn't stretch
DS9173C-13 April 2011
www.richtek.com
11
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| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet RT9173C.PDF ] | |
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