RDA5802H Datasheet PDF - RDA
| Part Number | RDA5802H | |
| Description | SINGLE-CHIP BROADCAST FM RADIO TUNER | |
| Manufacturers | RDA | |
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RDA5802H
SINGLE-CHIP BROADCAST FM RADIO TUNER
Rev.1.1–Aug.2010
1 General Description
The RDA5802H is a new generation single-chip
broadcast FM stereo radio tuner with fully
integrated synthesizer, IF selectivity and MPX
decoder. The tuner uses the CMOS process,
support multi-interface and require the least
external component. The package size is 4X4mm
and is completely adjustment-free. All these make
it very suitable for portable devices.
The RDA5802H has a powerful low-IF digital audio
processor, this make it have optimum sound quality
with varying reception conditions.
The RDA5802H can be tuned to the worldwide
frequency band, even support frequency range
50~65MHz.
1.1 Features
CMOS single-chip fully-integrated FM tuner
Low power consumption
Total current consumption lower than 21mA at 3.0V
power supply when under normal situation
Support worldwide frequency band
50 -108 MHz
Support flexible channel spacing mode
100KHz, 200KHz, 50KHz and 25KHz
Digital low-IF tuner
Image-reject down-converter
High performance A/D converter
IF selectivity performed internally
Fully integrated digital frequency synthesizer
Fully integrated on-chip RF and IF VCO
Fully integrated on-chip loop filter
Autonomous search tuning
Support 32.768KHz crystal oscillator
Digital auto gain control (AGC)
Figure 1-1. RDA5802H Top View
Digital adaptive noise cancellation
Mono/stereo switch
Soft mute
High cut
Programmable de-emphasis (50/75 s)
Receive signal strength indicator (RSSI) and SNR
Bass boost
Volume control and mute
I2S digital output interface
Line-level analog output voltage
32.768 KHz 12M,24M,13M,26M,19.2M,38.4MHz
Reference clock
2-wire and 3-wire serial control bus interface
Directly support 32Ω resistance loading
Integrated LDO regulator
1.8 to 5.5 V operation voltage
4X4mm 24 pin QFN package
Copyright © RDA Microelectronics Inc. 2006. All rights are reserved.
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA.
http://www.Datasheet4U.com
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RDA Microelectronics, Inc.
3.3 Delta-Sigma Synthesizer
The delta-sigma sy nthesizer ge nerates t he c onstant
clock signal to ADCs and DSP.
3.4 Power Supply
The RDA5802H integrated one LDO which
supplies power to the chip. The external supply
voltage range is 1.8-5.5 V.
3.5 RESET and Control Interface select
The RDA5802H is RESET itself When VIO is
Power up. And also support soft reset by trigger
02H BIT1 from 0 to 1. The control interface is
select by MODE Pin. The MODE Pin is low, I2C
Interface is select. The MODE Pin is set to VIO,
SPI Interface is select.
3.6 Control Interface
The RDA5802H supports three- wire and I2C
control interface. User could select either of them
to program the chip.
The three -wire interfa ce is a st andard SPI
interface. It inclu des three pins: SEN, SCLK and
SDIO. Each register write is 25-bit long, including
4-bit high register address, a r/w bit, 4-bit low
register address, and 16-bit data (MSB is the first
bit). RDA5802H samples command byte and data
at posed ge o f SCLK. Each registe r re ad is also
25-bit long, including 4-bit high register address, a
r/w bit, 4-bit low register address, and 16-bit data
(MSB is the first bit) from RDA5802H. The turn
around cycle between command byte from MCU
and data from RDA5802H is a half cycle.
RDA5802H samples command byte at posedge
of SCLK, and output data also at posedge of
SCLK.
The I 2C int erface is compliant to I 2C Bus
Specification 2.1. It include s two pins: SCLK and
SDIO. A I2C interface transfer begins with START
condition, a comman d byte and dat a bytes, each
byte has a followed ACK (or NACK) bit, and ends
with STOP condition. The command byte includes
a 7-bit chip address (00 10000b) and a R/W bit.
The ACK (or NACK) is always sent out by receiver.
When in write tran sfer, d ata bytes i s written o ut
from MCU, a nd when in read tran sfer, data bytes
is rea d out from RDA 5802H. The re is no visible
RDA5802H FM Tuner V1.1
register address in I2C interface transfers. The I2C
interface has a fixed start register address (0x02h
for write transfer and 0x0Ah for read transfer), and
an internal incremental address counter. If register
address meets the end of register file, 0x3Ah,
register address will wrap back to 0x00h. For write
transfer, MCU programs registers from register
0x02h high byte, then register 0x02h low byte,
then register 0x03h high byte, till the last register.
RDA5802H always gives out ACK after every byte,
and MCU gives out STOP condition when register
programming is finished. For read transfer, after
command byte from MCU, RDA5802H sends out
register 0x0Ah high byte, then register 0x0Ah low
byte, then register 0x0Bh high byte, till receives
NACK from MCU. MCU gives out ACK for data
bytes besides last data byte. MCU gives out
NACK for last data byte, and then RDA5802H will
return the bus to MCU, and MCU will give out
STOP condition.
Details refer to RDA5802H Programming Guide.
3.7 I2S Audio Data Interface
The RDA5802H supports I2S (Inter_IC Sound Bus)
audio interfa ce. The interface is fully compliant
with I2S bus specification. When setting I2SEN bit
high, RDA5802H will output SCK, WS, SD signals
from GPIO3, GPIO1, GPIO2 as I 2S m aster and
transmitter, the sampl e rate is 48Kbp s ，
44.1kbps,32kbps….. RDA5802 H al so support as
I2S slaver mode and tran smitter, the sample rate
is less than 100kbps.
Details refer to RDA5802H Programming Guide.
3.8 GPIO Outputs
The RDA5802H has three GPIOs. The function of
GPIOs could programmed with bits GPIO1[1:0],
GPIO2[1:0], GPIO3[1:0] and I2SEN.
If I2SEN is s et to low , GPIO pins c ould be
programmed to output low or high or high-Z, or be
programmed to output interru pt a nd ste reo
indicator with bits GPIO1[1:0], GPIO2[1:0],
GPIO3[1:0]. GPIO2 coul d be progra mmed to
output a low interrupt (inte rrupt will be gene rated
only with interrupt enable bit STCIEN is set to high)
when seek/tune process completes. GPIO3 could
be programmed to output stereo indicator bit ST.
Constant low, high or high-Z functionality is
available regardless of the state of VDD supplies
or the ENABLE bit.
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA.
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