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PDF H27UCG8T2BYR-BC Data sheet ( Hoja de datos )
| Número de pieza | H27UCG8T2BYR-BC | |
| Descripción | 64Gb(8192M x 8bit) MLC NAND Flash | |
| Fabricantes | Hynix | |
| Logotipo |  |
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H27UCG8T2BYR-BC
64Gb(8192M x 8bit) MLC NAND Flash
F20 64Gb MLC
NAND Flash Memory
Legacy LGA52
This document is a general product description and is subject to change without notice. SK hynix does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev 1.2 / Jun. 2012
1
http://www.Datasheet4U.com
1 page  
H27UCG8T2BYR-BC
64Gb(8192M x 8bit) MLC NAND Flash
3.18. Random Data Input Timings ………………………………………………………………………………… 34
3.19. Multi Plane Page Program Operation Timings ………………………………………………………….. 35
3.20.
3.21.
Copy-Back Program Operation Timings with Random Date Input .………………………………..
Cache Program Operation Timings …………………………………………………………………………
36
36
3.22. Multi Plane Cache Program Operation Timings …………………………………………………………. 37
3.23. Block Erase Operation Timings ……………………………………………………………………………… 37
3.24. Multi Plane Erase Operation Timings ...................................................................................... 38
3.25. Reset Timings …………………………………………………………………………………………………… 38
4. Device Operation …………………………………………………………………………………………………… 39
4.1. Page Read ………………………………………………………………………………………………………….. 39
4.2. Cache Read ………………………………………………………………………………………………………… 40
4.3. Cache Read Enhanced ………………………………………………………………………………………….. 40
4.4. Multi Plane Page Read ………………………………………………………………………………………….. 41
4.5. Multi Plane Cache Read ………………………………………………………………………………………... 42
4.6. Multi Plane Cache Read Enhanced ………………………………………………………………………….. 42
4.7. Read ID …………………………………………………………………………………………………………….. 43
4.8. Read Status Register ……………………………………………………………………………………………. 43
4.9. Page Program …………………………………………………………………………………………………….. 44
4.10. Multi Plane Program …………………………………………………………………………………………… 45
4.11. Cache Program .…………………………………………………………………………………………………. 46
4.12. Multi Plane Cache Program .…………………………………………………………………………………. 48
4.13. Copy-Back Program ……………………………………………………………………………………………. 49
4.14. Multi-Plane Copy-Back Program ……………………………………………………………………………. 50
4.15. Block Erase ……………………………………………………………………………………………………….. 51
4.16. Multi Plane Block Erase ……………………………………………………………………………………….. 52
4.17. Reset ………………………………………………………………………………………………………………. 52
5. Other Features ………………………………………………………………………………………………………… 53
5.1. Data Protection & Power on/off Sequence ………………………………………………………………… 53
5.2. Ready / Busy .……………………………………………………………………………………………………… 54
5.3. Write Protect Operation ………………………………………………………………………………………… 55
6. Application Notes and Comments ...…………….……………………….……………………………………… 56
6.1. Paired Page Address Information ..………………………………………………………………………….. 57
Rev 1.2 / Jun. 2012
5
5 Page 
1.5. Block Diagram
A15-A34
A0-A14
H27UCG8T2BYR-BC
64Gb(8192M x 8bit) MLC NAND Flash
VccQ
VssQ
Figure 3 : Block diagram(SDP)
1.6. Array Organization
CaCcahceherergeigstisetrer
DaDtaatarergeisgtiestrer
2110213610263224bbbllloooccckkk/s/ssd/p/epdlavleanicvneeiece
17,664 bytes
81,61,93284
16,384
1,280
1,280
1 Block
17,664 bytes
81,68,33284
81,68,33284
1,280
1,280
1 Block
I/O 7
I/O 0
1 Page = (16,384 + 1,280) bytes
1 Block = (16,384 + 1,280) bytes x 256 pages
= (4M+ 320K) bytes
1 Device = (16,384 + 1,280) bytes x 256 pages x 2,132 blocks
Plane 0
Plane 1
Figure 4 : Array organization
Rev 1.2 / Jun. 2012
11
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