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24LC080-ISN 데이터시트 PDF




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기능 8K/16K2.5VSPIOBusSerialEEPROM
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24LC080-ISN 데이터시트, 핀배열, 회로
25LC080/160
8K/16K 2.5V SPIBus Serial EEPROM
FEATURES
• SPI modes 0,0 and 1,1
• 3 MHz Clock Rate
• Single supply with programming operation down
to 2.5V
• Low Power CMOS Technology
- Max Write Current: 5 mA
- Read Current: 1.0 mA
- Standby Current: 1 µA typical
• Organization
- 1024 x 8 for 25LC080
- 2048 x 8 for 25LC160
• 16 Byte Page
• Sequential Read
• Self-timed ERASE and WRITE Cycles
• Block Write Protection
- Protect none, 1/4, 1/2, or all of Array
• Built-in Write Protection
- Power On/Off Data Protection Circuitry
- Write Latch
- Write Protect Pin
• High Reliability
- Endurance: 10M cycles (guaranteed)
- Data Retention: >200 years
- ESD protection: >4000 V
• 8-pin PDIP/SOIC Packages
• Temperature ranges supported
- Commercial (C): 0°C to +70°C
- Industrial (I): -40°C to +85°C
DESCRIPTION
The Microchip Technology Inc. 25LC080/160 are 8K
and 16K bit Serial Electrically Erasable PROMs. The
memory is accessed via a simple Serial Peripheral
Interface (SPI) compatible serial bus. The bus signals
required are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
There are two other inputs that provide the end user
with additional flexibility. Communication to the device
can be paused via the hold pin (HOLD). While the
device is paused, transitions on its inputs will be
ignored, with the exception of chip select, allowing the
host to service higher priority interrupts. Also, write
operations to the Status Register can be disabled via
the write protect pin (WP).
PACKAGE TYPES
PDIP
CS 1
SO 2
WP 3
VSS 4
SOIC
CS
SO
WP
VSS
1
2
3
4
BLOCK DIAGRAM
Status
Register
8 VCC
7 HOLD
6 SCK
5 SI
8 VCC
7 HOLD
6 SCK
5 SI
HV Generator
I/O Control
Logic
Memory
Control
Logic
X
Dec
EEPROM
Array
Page Latches
WP
SI
SO
CS
SCK
HOLD
Vcc
Vss
Y Decoder
Sense Amp.
R/W Control
SPI is a trademark of Motorola.
© 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS21145D-page 1




24LC080-ISN pdf, 반도체, 판매, 대치품
25LC080/160
TABLE 1-3: AC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted.
VCC = +2.5V to +5.5V
Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I):
Tamb = -40˚C to +85˚C
Symbol
Parameter
Min Max Units
Test Conditions
fSCK Clock Frequency
— 3 MHz VCC=4.5V to 5.5V
— 2 MHz VCC=2.5V to 4.5V
tCSS CS Setup Time
100 —
ns VCC=4.5V to 5.5V
250 —
ns VCC=2.5V to 4.5V
tCSH
CS Hold Time
100 —
ns VCC=4.5V to 5.5V
250 —
ns VCC=2.5V to 4.5V
tCSD
CS Disable Time
250 —
ns VCC=4.5V to 5.5V
500 —
ns VCC=2.5V to 4.5V
tSU Data Setup Time
30 —
ns VCC=4.5V to 5.5V
50 —
ns VCC=2.5V to 4.5V
tHD Data Hold Time
50 —
ns VCC=4.5V to 5.5V
100 —
ns VCC=2.5V to 4.5V
tR CLK Rise Time
—2
µs (Note 1)
tF CLK Fall Time
—2
µs (Note 1)
tHI Clock High Time
150 —
ns VCC=4.5V to 5.5V
250 —
ns VCC=2.5V to 4.5V
tLO Clock Low Time
150 —
ns VCC=4.5V to 5.5V
250 —
ns VCC=2.5V to 4.5V
tCLD Clock Delay Time
50 —
ns
tV Output Valid from
— 150
ns VCC=4.5V to 5.5V
Clock Low
— 250
ns VCC=2.5V to 4.5V
tHO Output Hold Time
0—
ns
tDIS Output Disable Time
— 200
ns VCC=4.5V to 5.5V (Note 1)
— 250
ns VCC=2.5V to 4.5V (Note 1)
tHS HOLD Setup Time
100 —
ns VCC=4.5V to 5.5V
100 —
ns VCC=2.5V to 4.5V
tHH HOLD Hold Time
100 —
ns VCC=4.5V to 5.5V
100 —
ns VCC=2.5V to 4.5V
tHZ
HOLD Low to Output High-Z
100
150 —
ns VCC=4.5V to 5.5V (Note 1)
ns VCC=2.5V to 4.5V (Note 1)
tHV
HOLD High to Output Valid
100
150 —
ns VCC=4.5V to 5.5V (Note 1)
ns VCC=2.5V to 4.5V (Note 1)
tWC Internal Write Cycle Time
—5
ms (Note 2)
— Endurance
10M — E/W Cycles 25°C, Vcc = 5.0V, Block Mode
(Note 3)
Note 1: This parameter is periodically sampled and not 100% tested.
2: tWC begins on the rising edge of CS after a valid write sequence and ends when the internal self-timed write
cycle is complete.
3: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
DS21145D-page 4
Preliminary
© 1996 Microchip Technology Inc.

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24LC080-ISN 전자부품, 판매, 대치품
25LC080/160
2.3 Write Status Register (WRSR)
The WRSR instruction allows the user to select one of
four protection options for the array by writing to the
appropriate bits in the status register. The array is
divided up into four segments. The user has the ability
to write protect none, one, two, or all four of the seg-
ments of the array. The partitioning is controlled as illus-
trated in table below.
See Figure for WRSR timing sequence.
TABLE 2-3: ARRAY PROTECTION
BP1
BP0
Array Addresses
Write Protected
00
none
01
upper 1/4
300h-3FFh for 25LC080
600h-7FFh for 25LC160
10
upper 1/2
200h-3FFh for 25LC080
400h-7FFh for 25LC160
11
all
000h-3FFh for 25LC080
000h-7FFh for 25LC160
3.0 DEVICE OPERATION
3.1 Clock and Data Timing
Data input on the SI pin is latched on the rising edge of
SCK. Data is output on the SO pin after the falling edge
of SCK.
3.2 Read Sequence
The part is selected by pulling CS low. The 8-bit read
instruction is transmitted to the 25LC080/160 followed
by the 16-bit address, with the five (25LC160) or six
(25LC080) MSBs of the address being don’t care bits.
After the correct read instruction and address are sent,
the data stored in the memory at the selected address
is shifted out on the SO pin. The data stored in the
memory at the next address can be read sequentially
by continuing to provide clock pulses. The internal
address pointer is automatically incremented to the
next higher address after each byte of data is shifted
out. When the highest address is reached ($3FF for
25LC080, $7FF for 25LC160) the address counter rolls
over to address $000 allowing the read cycle to be con-
tinued indefinitely. The read operation is terminated by
setting CS high (see Figure 3-1).
3.3 Write Sequence
Prior to any attempt to write data to the 25LC080/160,
the write enable latch must be set by issuing the WREN
instruction (Figure 3-2). This is done by setting CS low
and then clocking the proper instruction into the
25LC080/160. After all eight bits of the instruction are
transmitted, the CS must be brought high to set the
write enable latch. If the write operation is initiated
immediately after the WREN instruction without CS
being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set.
Once the write enable latch is set, the user may pro-
ceed by setting the CS low, issuing a write instruction,
followed by the 16-bit address, with the five (25LC160)
or six (25LC080) MSBs of the address being don’t care
bits, and then the data to be written. Up to 16 bytes of
data can be sent to the 25LC080/160 before a write
cycle is necessary. The only restriction is that all of the
bytes must reside in the same page. A page address
begins with XXXX XXXX XXXX 0000 and ends with
XXXX XXXX XXXX 1111. If the internal address
counter reaches XXXX XXXX XXXX 1111 and the
clock continues, the counter will roll back to the first
address of the page and overwrite any data in the page
that may have been written.
For the data to be actually written to the array, the CS
must be brought high after the least significant bit (D0)
of the nth data byte has been clocked in. If CS is brought
high at any other time, the write operation will not be
completed. Refer to Figure 3-3 and Figure 3-4 for more
detailed illustrations on the byte write sequence and the
page write sequence, respectively.
While the write is in progress, the status register may
be read to check the status of the WPEN, WIP, WEL,
BP1, and BP0 bits. A read attempt of a memory array
location will not be possible during a write cycle. When
a write cycle is completed, the write enable latch is
reset
3.4 Data Protection
The following protection has been implemented to pre-
vent inadvertent writes to the array:
• The write enable latch is reset on power-up.
• A write enable instruction must be issued to set
the write enable latch.
• After a successful byte write, page write, or status
register write, the write enable latch is reset.
• CS must be set high after the proper number of
clock cycles to start an internal write cycle.
• Access to the array during an internal write cycle
is ignored and programming is continued.
3.5 Power On State
The 25LC080/160 powers on in the following state:
• The device is in low power standby mode (CS=1).
• The write enable latch is reset.
• SO is in high impedance state.
• A low level on CS is required to enter active state.
© 1996 Microchip Technology Inc.
Preliminary
DS21145D-page 7

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8K/16K2.5VSPIOBusSerialEEPROM

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