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PDF 24LC08B Data sheet ( Hoja de datos )
| Número de pieza | 24LC08B | |
| Descripción | 8K I2C Serial EEPROM | |
| Fabricantes | MicrochipTechnology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 24LC08B (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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24AA08/24LC08B
8K I2C™ Serial EEPROM
Device Selection Table
Part
Number
VCC
Range
Max. Clock
Frequency
24AA08
1.7-5.5
400 kHz(1)
24LC08B 2.5-5.5
400 kHz
Note 1: 100 kHz for VCC <2.5V
Temp.
Ranges
I
I, E
Features:
• Single Supply with Operation down to 1.7V for
24AA08 Devices, 2.5V for 24LC08B Devices
• Low-Power CMOS Technology:
- Read current 1 mA, max.
- Standby current 1 μA, max
• 2-Wire Serial Interface, I2C™ Compatible
• Schmitt Trigger inputs for Noise Suppression
• Output Slope Control to eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 3 ms, typical
• Self-Timed Erase/Write Cycle
• 16-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 years
• Factory Programming Available
• Packages include 8-lead PDIP, SOIC, TSSOP,
DFN, TDFN, MSOP and 5-lead SOT-23
• Pb-Free and RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
*24XX08 is used in this document as a generic part
number for the 24AA08/24LC08B devices.
Description:
The Microchip Technology Inc. 24AA08/24LC08B
(24XX08*) is a 8 Kbit Electrically Erasable PROM. The
device is organized as four blocks of 256 x 8-bit
memory with a 2-wire serial interface. Low-voltage
design permits operation down to 1.7V, with standby
and active currents of only 1 μA and 1 mA,
respectively. The 24XX08 also has a page write
capability for up to 16 bytes of data. The 24XX08 is
available in the standard 8-pin PDIP, surface mount
SOIC, TSSOP, 2x3 DFN, 2x3 TDFN and MSOP
packages, and is also available in the 5-lead SOT-23
package. All packages are Pb-free and RoHS
compliant.
Block Diagram
HV
WP Generator
I/O
Control
Logic
I/O
SCL
SDA
VCC
VSS
Memory
Control
Logic
XDEC
EEPROM
Array
Page
Latches
YDEC
Sense Amp.
R/W Control
Package Types
PDIP, MSOP
SOIC, TSSOP
A0 1
A1 2
A2 3
VSS 4
8 VCC A0
7 WP A1
6 SCL A2
5 SDA VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
SOT-23-5
DFN/TDFN
SCL 1
Vss
SDA
2
3
5 WP
4 Vcc
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
Note:
Pins A0, A1 and A2 are not used by the 24XX08. (No
internal connections).
© 2009 Microchip Technology Inc.
DS21710J-page 1
1 page  
24AA08/24LC08B
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
Name
A0
A1
A2
VSS
SDA
SCL
WP
VCC
PDIP
1
2
3
4
5
6
7
8
SOIC
1
2
3
4
5
6
7
8
TSSOP
1
2
3
4
5
6
7
8
DFN
1
2
3
4
5
6
7
8
TDFN
1
2
3
4
5
6
7
8
MSOP
1
2
3
4
5
6
7
8
SOT-23
Description
— Not Connected
— Not Connected
— Not Connected
2 Ground
3 Serial Address/Data I/O
1 Serial Clock
5 Write-Protect Input
4 +1.7V to 5.5V Power Supply
2.1 Serial Address/Data Input/Output
(SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. Since it is an open-
drain terminal, the SDA bus requires a pull-up resistor
to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for 400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating Start and Stop conditions.
2.2 Serial Clock (SCL)
The SCL input is used to synchronize the data transfer
to and from the device.
2.3 Write-Protect (WP)
The WP pin must be connected to either VSS or VCC.
If tied to VSS, normal memory operation is enabled
(read/write the entire memory 000-3FF).
If tied to VCC, write operations are inhibited. The entire
memory will be write-protected. Read operations are
not affected.
2.4 A0, A1, A2
The A0, A1 and A2 pins are not used by the 24XX08.
They may be left floating or tied to either VSS or VCC.
© 2009 Microchip Technology Inc.
DS21710J-page 5
5 Page 
24AA08/24LC08B
FIGURE 8-2:
RANDOM READ
Bus Activity
Master
S
T Control
A
R
Byte
T
Word
Address (n)
SDA Line
Bus Activity
S 1 0 1 0 XB1B00
Block
A
C
Select K
Bits
x = “don’t care”
S
T Control
A
R
Byte
T
S 1 0 1 0 XB1B01
A
C
Block
A
C
K Select K
Bits
Data (n)
S
T
O
P
P
N
o
A
C
K
FIGURE 8-3:
Bus Activity
Master
SDA Line
Bus Activity
SEQUENTIAL READ
Control
Byte
Data (n)
Data (n + 1)
Data (n + 2)
1
AA AA
CC CC
KK KK
Data (n + X)
S
T
O
P
P
N
o
A
C
K
© 2009 Microchip Technology Inc.
DS21710J-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 24LC08B.PDF ] | |
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