|
|
PDF ADF4360-9 Data sheet ( Hoja de datos )
| Número de pieza | ADF4360-9 | |
| Descripción | Clock Generator PLL | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ADF4360-9 (archivo pdf) en la parte inferior de esta página. Total 25 Páginas | ||
|
No Preview Available !
Data Sheet
Clock Generator PLL with Integrated VCO
ADF4360-9
FEATURES
GENERAL DESCRIPTION
Primary output frequency range: 65 MHz to 400 MHz
Auxiliary divider from 2 to 31, output from 1.1 MHz to 200 MHz
3.0 V to 3.6 V power supply
1.8 V logic compatibility
Integer-N synthesizer
Programmable output power level
3-wire serial interface
Digital lock detect
Software power-down mode
APPLICATIONS
System clock generation
Test equipment
Wireless LANs
CATV equipment
The ADF4360-9 is an integrated integer-N synthesizer and
voltage-controlled oscillator (VCO). External inductors set the
ADF4360-9 center frequency. This allows a VCO frequency
range of between 65 MHz and 400 MHz.
An additional divider stage allows division of the VCO signal.
The CMOS level output is equivalent to the VCO signal divided
by the integer value between 2 and 31. This divided signal can
be further divided by 2, if desired.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging
from 3.0 V to 3.6 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
RSET
REFIN
ADF4360-9
14-BIT R
COUNTER
CLK
DATA
LE
24-BIT DATA
REGISTER
24-BIT
FUNCTION
LATCH
LOCK
DETECT
MUTE
CHARGE
PHASE
PUMP
COMPARATOR
LD
CP
VVCO
VTUNE
L1
L2
CC
CN
13-BIT B
COUNTER
N=B
VCO
CORE
OUTPUT
STAGE
RFOUTA
RFOUTB
DIVIDE-BY-A
(2 TO 31)
DIVIDE-BY-2
MULTIPLEXER
AGND
DGND
Figure 1.
CPGND
DIVOUT
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2008–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADF4360-9
Data Sheet
Parameter
Harmonic Content (Third)
Output Power5, 7
Output Power5, 8
Output Power Variation
VCO Tuning Range
VCO NOISE CHARACTERISTICS
VCO Phase Noise Performance9,10
B Version
−21
−9/0
Unit
dBc typ
dBm typ
−14/−9
dBm typ
±3
1.25/2.5
dB typ
V min/V max
−91
−117
−139
−140
−147
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
Test Conditions/Comments
Using tuned load, programmable in 3 dB steps;
see Figure 35
Using 50 Ω resistors to VVCO, programmable in
3 dB steps; see Figure 33
At 10 kHz offset from carrier
At 100 kHz offset from carrier
At 1 MHz offset from carrier
At 3 MHz offset from carrier
At 10 MHz offset from carrier
Normalized In-Band Phase Noise 10, 11
In-Band Phase Noise10, 11
RMS Integrated Jitter12
Spurious Signals Due to PFD Frequency13
DIVOUT CHARACTERISTICS12
Integrated Jitter Performance
(Integrated from 100 Hz to 1 GHz)
DIVOUT = 180 MHz
DIVOUT = 95 MHz
DIVOUT = 80 MHz
DIVOUT = 52 MHz
DIVOUT = 45 MHz
DIVOUT = 10 MHz
DIVOUT Duty Cycle
A Output
A/2 Output
−218
−110
1.4
−75
1.4
1.4
1.4
1.4
1.4
1.6
1/A × 100
50
dBc/Hz typ
dBc/Hz typ
ps typ
dBc typ
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
% typ
% typ
At 1 kHz offset from carrier
Measured at RFOUTA
VCO frequency = 320 MHz to 380 MHz
A = 2, A output selected
A = 2, A/2 output selected
A = 2, A/2 output selected
A = 3, A/2 output selected (VCO = 312 MHz,
PFD = 1.6 MHz)
A = 4, A/2 output selected
A = 18, A/2 output selected (VCO = 360 MHz,
PFD = 1.6 MHz)
Divide-by-A selected
Divide-by-A/2 selected
1 Operating temperature range is −40°C to +85°C.
2 Guaranteed by design. Sample tested to ensure compliance.
3 ICP is internally modified to maintain constant loop gain over the frequency range.
4 TA = 25°C; AVDD = DVDD = VVCO = 3.3 V.
5 Unless otherwise stated, these characteristics are guaranteed for VCO core power = 5 mA. L1, L2 = 270 nH, 470 Ω resistors to GND in parallel with L1, L2.
6 Jumping from 90 MHz to 108 MHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz.
7 For more detail on using tuned loads, see the Output Matching section.
8 Using 50 Ω resistors to VVCO into a 50 Ω load.
9 The noise of the VCO is measured in open-loop conditions. L1, L2 = 56 nH.
10 The phase noise is measured with the EV-ADF4360-9EB1Z evaluation board and the Agilent E5052A signal source analyzer.
11 fREFIN = 10 MHz; fPFD = 1 MHz; N = 360; loop bandwidth = 40 kHz. The normalized phase noise floor is estimated by measuring the in-band phase noise at the output of
the VCO and subtracting 20logN (where N is the N divider value) and 10logfPFD. PNSYNTH = PNTOT − 10logfPFD − 20logN.
12 The jitter is measured with the EV-ADF4360-9EB1Z evaluation board and the Agilent E5052A signal source analyzer. A low noise TCXO provides the REFIN for the
synthesizer, and the jitter is measured over the instrument’s jitter measurement bandwidth. fREFIN = 10 MHz; fPFD = 1 MHz; N = 360; loop bandwidth = 40 kHz, unless
otherwise noted.
13 The spurious signals are measured with the EV-ADF4360-9EB1Z evaluation board and the Agilent E5052A signal source analyzer. The spectrum analyzer provides the
REFIN for the synthesizer; fREFIN = 10 MHz at 0 dBm. fREFIN = 10 MHz; fPFD = 1 MHz; N = 360; loop bandwidth = 40 kHz.
Rev. D | Page 4 of 24
5 Page 
ADF4360-9
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 16. SW1 and SW2
are normally closed switches, and SW3 is normally open. When
power-down is initiated, SW3 is closed, and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin at
power-down.
POWER-DOWN
CONTROL
NC 100kΩ
REFIN NC
SW2
SW1
SW3
NO
TO R COUNTER
BUFFER
Figure 16. Reference Input Stage
N COUNTER
The CMOS N counter allows a wide division ratio in the PLL
feedback counter. The counters are specified to work when the
VCO output is 400 MHz or less. To avoid confusion, this is
referred to as the B counter. It makes it possible to generate
output frequencies that are spaced only by the reference
frequency divided by R. The VCO frequency equation is
fVCO = B × fREFIN/R
where:
fVCO is the output frequency of the VCO.
B is the preset divide ratio of the binary 13-bit counter (3 to 8191).
fREFIN is the external reference frequency oscillator.
R COUNTER
The 14-bit R counter allows the input reference frequency
to be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
PFD AND CHARGE PUMP
The PFD takes inputs from the R counter and N counter (N = B)
and produces an output proportional to the phase and frequency
difference between them. Figure 17 is a simplified schematic.
The PFD includes a programmable delay element that controls
the width of the antibacklash pulse. This pulse ensures that
there is no dead zone in the PFD transfer function and
minimizes phase noise and reference spurs. Two bits in the R
counter latch, ABP2 and ABP1, control the width of the pulse
(see Figure 25).
Data Sheet
HI
R DIVIDER
D1 Q1 UP
U1
CLR1
PROGRAMMABLE
DELAY
U3
ABP1
ABP2
HI
N DIVIDER
CLR2
DOWN
D2 Q2
U2
VP CHARGE
PUMP
CP
CPGND
R DIVIDER
N DIVIDER
CP OUTPUT
Figure 17. PFD Simplified Schematic and Timing (In Lock)
LOCK DETECT
The LD pin outputs a lock detect signal. Digital lock detect is
active high. When lock detect precision (LDP) in the R counter
latch is set to 0, digital lock detect is set high when the phase error
on three consecutive phase detector cycles is <15 ns.
When LDP is set to 1, five consecutive cycles of <15 ns phase
error are required to set the lock detect. It stays set high until a
phase error of >25 ns is detected on any subsequent PD cycle.
INPUT SHIFT REGISTER
The digital section of the ADF4360-9 includes a 24-bit input
shift register, a 14-bit R counter, and an 18-bit N counter,
comprising a 5-bit A counter and a 13-bit B counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. The two LSBs, DB1 and DB0,
are shown in Figure 2.
Rev. D | Page 10 of 24
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet ADF4360-9.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ADF4360-0 | Integrated Synthesizer and VCO | Analog Devices |
| ADF4360-1 | Integrated Synthesizer and VCO | Analog Devices |
| ADF4360-2 | Integrated Synthesizer and VCO | Analog Devices |
| ADF4360-3 | Integrated Synthesizer and VCO | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |