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24LC21 데이터시트 PDF




MicrochipTechnology에서 제조한 전자 부품 24LC21은 전자 산업 및 응용 분야에서
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부품번호 24LC21 기능
기능 1K2.5VDualModeI2CSerialEEPROM
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24LC21 데이터시트, 핀배열, 회로
Not recommended for new designs –
Please use 24LCS21A.
24LC21
1K 2.5V Dual Mode I2CSerial EEPROM
Features:
• Single supply with operation down to 2.5V
• Completely implements DDC1/DDC2interface
for monitor identification
• Low-power CMOS technology:
- 1 mA active current typical
- 10 µA standby current typical at 5.5V
• 2-wire serial interface bus, I2Ccompatible
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Factory programming (QTP) available
• 1,000,000 erase/write cycles ensured
• Data retention > 200 years
• 8-pin PDIP and SOIC package
• Available for extended temperature ranges
Commercial (C):
Industrial (I):
0°C to +70°C
-40°C to +85°C
Description:
The Microchip Technology Inc. 24LC21 is a 128 x 8 bit
Electrically Erasable PROM. This device is designed
for use in applications requiring storage and serial
transmission of configuration and control information.
Two modes of operation have been implemented:
Transmit-only mode and Bidirectional mode. Upon
power-up, the device will be in the Transmit-only mode,
sending a serial bit stream of the entire memory array
contents, clocked by the VCLK pin. A valid high-to-low
transition on the SCL pin will cause the device to enter
the Bidirectional mode, with byte selectable read/write
capability of the memory array. The 24LC21 is available
in a standard 8-pin PDIP and SOIC package, in both
commercial and industrial temperature ranges.
Package Types
PDIP
NC 1
NC 2
NC 3
VSS 4
SOIC
NC 1
NC 2
NC 3
VSS
4
8 VCC
7 VCLK
6 SCL
5 SDA
8 VCC
7 VCLK
5 SCL
5 SDA
Block Diagram
VCLK
I/O
Control
Logic
Memory
Control
Logic
XDEC
SDA SCL
VCC
VSS
HV Generator
EEPROM
Array
Page Latches
YDEC
Sense Amp
R/W Control
I2C is a trademark of Philips Corporation.
DDC is a trademark of the Video Electronics Standards Association.
2004 Microchip Technology Inc.
DS21095J-page 1




24LC21 pdf, 반도체, 판매, 대치품
24LC21
2.0 FUNCTIONAL DESCRIPTION
The 24LC21 operates in two modes, the Transmit-only
mode and the Bidirectional mode. There is a separate
two wire protocol to support each mode, each having a
separate clock input and sharing a common data line
(SDA). The device enters the Transmit-only mode upon
power-up. In this mode, the device transmits data bits
on the SDA pin in response to a clock signal on the
VCLK pin. The device will remain in this mode until a
valid high-to-low transition is placed on the SCL input.
When a valid transition on SCL is recognized, the
device will switch into the Bidirectional mode. The only
way to switch the device back to the Transmit-only
mode is to remove power from the device.
2.1 Transmit-only Mode
The device will power-up in the Transmit-only mode.
This mode supports a unidirectional two wire protocol
for transmission of the contents of the memory array.
This device requires that it be initialized prior to valid
data being sent in the Transmit-only mode (see Initial-
ization Procedure, below). In this mode, data is trans-
FIGURE 2-1:
TRANSMIT-ONLY MODE
mitted on the SDA pin in 8-bit bytes, each followed by
a ninth, null bit (see Figure 2-1). The clock source for
the Transmit-only mode is provided on the VCLK pin,
and a data bit is output on the rising edge on this pin.
The eight bits in each byte are transmitted Most Signif-
icant bit first. Each byte within the memory array will be
output in sequence. When the last byte in the memory
array is transmitted, the output will wrap around to the
first location and continue. The Bidirectional mode
Clock (SCL) pin must be held high for the device to
remain in the Transmit-only mode.
2.2 Initialization Procedure
After VCC has stabilized, the device will be in the Trans-
mit-only mode. Nine clock cycles on the VCLK pin must
be given to the device for it to perform internal synchro-
nization. During this period, the SDA pin will be in a
high-impedance state. On the rising edge of the tenth
clock cycle, the device will output the first valid data bit
which will be the Most Significant bit of a byte. The
device will power-up at an indeterminate byte address.
(Figure 2-2).
SCL
TVAA
TVAA
SDA
Bit 1 (LSB)
Null Bit
Bit 1 (MSB)
Bit 7
VCLK
FIGURE 2-2:
VCC
SCL
TVHIGH
TVLOW
DEVICE INITIALIZATION
SDA
VCLK
High-impedance for 9 clock cycles
TVPU
12
8
TVAA
TVAA
Bit 8
Bit 7
9 10 11
DS21095J-page 4
2004 Microchip Technology Inc.

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24LC21 전자부품, 판매, 대치품
3.1.6 SLAVE ADDRESS
After generating a Start condition, the bus master trans-
mits the slave address consisting of a 7-bit device code
1010’ for the 24LC21, followed by three “don’t care”
bits.
The eighth bit of slave address determines if the master
device wants to read or write to the 24LC21 (Figure 3-5).
The 24LC21 monitors the bus for its corresponding
slave address all the time. It generates an
Acknowledge bit if the slave address was true and it is
not in a programming mode.
Operation Control Code
Read
Write
1010
1010
Chip Select
xxx
xxx
R/W
1
0
FIGURE 3-5:
Start
CONTROL BYTE
ALLOCATION
Read/Write
SLAVE ADDRESS
R/W A
1010xx x
24LC21
4.0 WRITE OPERATION
4.1 Byte Write
Following the Start signal from the master, the slave
address (4 bits), the “don’t care” bits (3 bits) and the
R/W bit which is a logic low, is placed onto the bus by
the master transmitter. This indicates to the
addressed slave receiver that a byte with a word
address will follow after it has generated an Acknowl-
edge bit during the ninth clock cycle. Therefore, the
next byte transmitted by the master is the word
address and will be written into the address pointer of
the 24LC21. After receiving another Acknowledge
signal from the 24LC21 the master device will transmit
the data word to be written into the addressed mem-
ory location. The 24LC21 acknowledges again and
the master generates a Stop condition. This initiates
the internal write cycle, and during this time the
24LC21 will not generate Acknowledge signals
(Figure 4-1).
It is required that VCLK be held at a logic high level in
order to program the device. This applies to byte write
and page write operation. Note that VCLK can go low
while the device is in its self-timed program operation
and not affect programming.
4.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LC21 in the same way as
in a byte write. But instead of generating a Stop condi-
tion the master transmits up to eight data bytes to the
24LC21, which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a Stop condition. After the
receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order five bits of the word address remains
constant. If the master should transmit more than eight
words prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received an
internal write cycle will begin (Figure 4-3).
2004 Microchip Technology Inc.
DS21095J-page 7

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