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24LC21A-P 데이터시트 PDF




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부품번호 24LC21A-P 기능
기능 1K2.5VDualModeI2CSerialEEPROM
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24LC21A-P 데이터시트, 핀배열, 회로
24LC21A
1K 2.5V Dual Mode I2CSerial EEPROM
FEATURES
• Single supply with operation down to 2.5V
• Completely implements DDC1/DDC2
interface for monitor identification, including recov-
ery to DDC1
• Pin and function compatible with 24LC21
• Low power CMOS technology
- 1 mA typical active current
- 10 µA standby current typical at 5.5V
• 2-wire serial interface bus, I2Ccompatible
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to eight bytes
• 10,000,000 erase/write cycles guaranteed
• Data retention > 200 years
• ESD Protection > 4000V
• 8-pin PDIP and SOIC package
• Available for extended temperature ranges
- Commercial (C):
0°C to +70°C
- Industrial (I):
-40°C to +85°C
DESCRIPTION
The Microchip Technology Inc. 24LC21A is a 128 x 8-
bit dual-mode Electrically Erasable PROM. This device
is designed for use in applications requiring storage
and serial transmission of configuration and control
information. Two modes of operation have been imple-
mented: Transmit-Only Mode and Bi-directional Mode.
Upon power-up, the device will be in the Transmit-Only
Mode, sending a serial bit stream of the memory array
from 00h to 7Fh, clocked by the VCLK pin. A valid high
to low transition on the SCL pin will cause the device to
enter the transition mode, and look for a valid control
byte on the I2C bus. If it detects a valid control byte from
the master, it will switch into Bi-directional Mode, with
byte selectable read/write capability of the memory
array using SCL. If no control byte is received, the
device will revert to the Transmit-Only Mode after it
receives 128 consecutive VCLK pulses while the SCL
pin is idle. The 24LC21A is available in a standard 8-pin
PDIP and SOIC package in both commercial and
industrial temperature ranges.
PACKAGE TYPES
PDIP
NC 1
NC 2
NC 3
VSS 4
SOIC
8 VCC
7 VCLK
6 SCL
5 SDA
NC 1
NC 2
NC 3
VSS 4
BLOCK DIAGRAM
8 VCC
7 VCLK
6 SCL
5 SDA
HV GENERATOR
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
XDEC
SDA SCL
VCLK
VCC
VSS
EEPROM
ARRAY
PAGE LATCHES
YDEC
SENSE AMP
R/W CONTROL
DDC is a trademark of the Video Electronics Standards Association.
I2C is a trademark of Philips Corporation.
© 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS21160B-page 1




24LC21A-P pdf, 반도체, 판매, 대치품
24LC21A
2.0 FUNCTIONAL DESCRIPTION
The 24LC21A is designed to comply to the DDC Stan-
dard proposed by VESA (Figure 3-3) with the exception
that it is not Access.bus capable. It operates in two
modes, the Transmit-Only Mode and the Bi-directional
Mode. There is a separate 2-wire protocol to support
each mode, each having a separate clock input but
sharing a common data line (SDA). The device enters
the Transmit-Only Mode upon power-up. In this mode,
the device transmits data bits on the SDA pin in
response to a clock signal on the VCLK pin. The device
will remain in this mode until a valid high to low transi-
tion is placed on the SCL input. When a valid transition
on SCL is recognized, the device will switch into the Bi-
directional Mode and look for its control byte to be sent
by the master. If it detects its control byte, it will stay in
the Bi-directional Mode. Otherwise, it will revert to the
Transmit-Only Mode after it sees 128 VCLK pulses.
2.1 Transmit-Only Mode
The device will power up in the Transmit-Only Mode at
address 00H. This mode supports a unidirectional
2-wire protocol for continuous transmission of the
contents of the memory array. This device requires that
it be initialized prior to valid data being sent in the Trans-
mit-Only Mode (Section 2.2). In this mode, data is
transmitted on the SDA pin in 8-bit bytes, with each byte
followed by a ninth, null bit (Figure 2-1). The clock
source for the Transmit-Only Mode is provided on the
VCLK pin, and a data bit is output on the rising edge on
this pin. The eight bits in each byte are transmitted most
significant bit first. Each byte within the memory array
will be output in sequence. After address 7Fh in the
memory array is transmitted, the internal address point-
ers will wrap around to the first memory location (00h)
and continue. The Bi-directional Mode Clock (SCL) pin
must be held high for the device to remain in the
Transmit-Only Mode.
2.2 Initialization Procedure
After VCC has stabilized, the device will be in the
Transmit-Only Mode. Nine clock cycles on the VCLK pin
must be given to the device for it to perform internal
sychronization. During this period, the SDA pin will be
in a high impedance state. On the rising edge of the
tenth clock cycle, the device will output the first valid
data bit which will be the most significant bit in address
00h. (Figure 2-2).
FIGURE 2-1: TRANSMIT-ONLY MODE
SCL
Tvaa
Tvaa
SDA
Bit 1 (LSB)
Null Bit
Bit 1 (MSB) Bit 7
VCLK
Tvhigh Tvlow
FIGURE 2-2: DEVICE INITIALIZATION
Vcc
SCL
SDA
VCLK
High Impedance for 9 clock cycles
Tvpu
12
8
Tvaa Tvaa
Bit 8
Bit 7
9 10 11
DS21160B-page 4
Preliminary
© 1996 Microchip Technology Inc.

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24LC21A-P 전자부품, 판매, 대치품
24LC21A
3.1 Bi-directional Mode Bus
Characteristics
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-4).
3.1.1 BUS NOT BUSY (A)
Both data and clock lines remain HIGH.
3.1.2 START DATA TRANSFER (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.1.3 STOP DATA TRANSFER (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.1.4 DATA VALID (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last
eight will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.
Note:
Once switched into Bi-directional Mode, the
24LC21A will remain in that mode until
power is removed. Removing power is the
only way to reset the 24LC21A into the
Transmit-only mode.
3.1.5 ACKNOWLEDGE
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note:
The 24LC21A does not generate any
acknowledge bits if an internal
programming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
FIGURE 3-4: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A) (B) (D) (D)
SCL
(C) (A)
SDA
START
CONDITION
ADDRESS OR
DATA
ACKNOWLEDGE ALLOWED
VALID
TO CHANGE
STOP
CONDITION
© 1996 Microchip Technology Inc.
Preliminary
DS21160B-page 7

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