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24LC32 데이터시트 PDF




MicrochipTechnology에서 제조한 전자 부품 24LC32은 전자 산업 및 응용 분야에서
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부품번호 24LC32 기능
기능 32KI2CSerialEEPROMinISOMicromodule
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24LC32 데이터시트, 핀배열, 회로
M 24LC32A MODULE
32K I2C™ Serial EEPROM in ISO Micromodule
FEATURES
• ISO 7816 compliant contact locations
• Single supply with operation down to 2.5V
- Maximum write current 3 mA at 6.0V
- Maximum read current 150 µA at 6.0V
- Standby current 1 µA max at 2.5V
• Two wire serial interface bus, I2Ccompatible
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Self-timed ERASE and WRITE cycles
• Power on/off data protection circuitry
• 1,000,000 ERASE/WRITE cycles guaranteed
• 32 byte page or byte write modes available
• Schmitt trigger inputs for noise suppression
• Output slope control to eliminate ground bounce
• 2 ms typical write cycle time, byte or page
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP and SOIC packages
• Temperature ranges:
- Commercial:
0˚C to +70˚C
DESCRIPTION
The Microchip Technology Inc. 24LC32A is a 4K x 8
(32K bit) Serial Electrically Erasable PROM in an ISO
micromodule for use in smart card applications. The
device has a page-write capability of up to 32 bytes.
ISO MODULE LAYOUT
VDD
VSS
SCL SDA
BLOCK DIAGRAM
HV GENERATOR
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
I/O
SCL
SDA
VCC
VSS
XDEC
EEPROM
ARRAY
PAGE LATCHES
YDEC
SENSE AMP
R/W CONTROL
I2C is a trademark of Philips Corporation.
© 1997 Microchip Technology Inc.
DS21225A-page 1




24LC32 pdf, 반도체, 판매, 대치품
24LC32A MODULE
2.0 PIN DESCRIPTIONS
2.1 SDA (Serial Data)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to VCC (typical 10Kfor 100 kHz, 1Kfor 400
kHz)
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
2.2 SCL (Serial Clock)
This input is used to synchronize the data transfer from
and to the device.
3.0 FUNCTIONAL DESCRIPTION
The 24LC32A supports a bidirectional two-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a
device receiving data as receiver. The bus must be con-
trolled by a master device which generates the serial
clock (SCL), controls the bus access, and generates
the START and STOP conditions, while the 24LC32A
works as slave. Both master and slave can operate as
transmitter or receiver but the master device deter-
mines which mode is activated.
DS21225A-page 4
© 1997 Microchip Technology Inc.

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24LC32 전자부품, 판매, 대치품
6.0 WRITE OPERATIONS
6.1 Byte Write
Following the start condition from the master, the con-
trol code (four bits), the device select (three bits), and
the R/W bit which is a logic low are clocked onto the bus
by the master transmitter. This indicates to the
addressed slave receiver that a byte with a word
address will follow after it has generated an acknowl-
edge bit during the ninth clock cycle. Therefore the next
byte transmitted by the master is the high-order byte of
the word address and will be written into the address
pointer of the 24LC32A MODULE. The next byte is the
least significant address byte. After receiving another
acknowledge signal from the 24LC32A the master
device will transmit the data word to be written into the
addressed memory location.
The 24LC32A acknowledges again and the master
generates a stop condition. This initiates the internal
write cycle, and during this time the 24LC32A will not
generate acknowledge signals (see Figure 6-1).
24LC32A MODULE
6.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LC32A in the same way
as in a byte write. But instead of generating a stop con-
dition, the master transmits up to 32 bytes which are
temporarily stored in the on-chip page buffer and will be
written into memory after the master has transmitted a
stop condition. After receipt of each word, the five lower
address pointer bits are internally incremented by one.
If the master should transmit more than 32 bytes prior
to generating the stop condition, the address counter
will roll over and the previously received data will be
overwritten. As with the byte write operation, once the
stop condition is received, an internal write cycle will
begin. (see Figure 6-2).
FIGURE 6-1: BYTE WRITE
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A CONTROL
R BYTE
T
ADDRESS
HIGH BYTE
ADDRESS
LOW BYTE
101 0 0 000 0 0 0 0
A
C
K
A
C
K
A
C
K
DATA
S
T
O
P
A
C
K
FIGURE 6-2: PAGE WRITE
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A CONTROL
R BYTE
T
ADDRESS
HIGH BYTE
101 0 0 000 0 0 0 0
A
C
K
A
C
K
ADDRESS
LOW BYTE
DATA BYTE 0
AA
CC
KK
DATA BYTE 31
S
T
O
P
A
C
K
© 1997 Microchip Technology Inc.
DS21225A-page 7

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