24LC320-IST Datasheet PDF - MicrochipTechnology
| Part Number | 24LC320-IST | |
| Description | 32K2.5VSPIBusSerialEEPROM | |
| Manufacturers | MicrochipTechnology | |
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25LC320
32K 2.5V SPI™ Bus Serial EEPROM
FEATURES
• SPI modes 0,0 and 1,1
• 3.0 MHz Clock Rate
• Single supply with Programming Operation down
to 2.5V
• Low Power CMOS Technology
- Max Write Current: 5.0 mA
- Read Current: 1 mA at 5.5V, 3 Mhz
- Standby Current: 1 µA typical
• 4096 x 8 Organization
• 32-Byte Page
• Sequential Read
• Self-timed ERASE and WRITE Cycles
• Block Write Protection
- Protect none, 1/4, 1/2, or all of Array
• Built-in Write Protection
- Power On/Off Data Protection Circuitry
- Write Enable Latch
- Write Protect Pin
• High Reliability
- Endurance: 1M cycles (guaranteed)
- Data Retention: >200 years
- ESD protection: >4000V
• 8-pin PDIP/SOIC, 14-pin TSSOP
• Temperature ranges supported
- Commercial (C):
0°C to +70°C
- Industrial (I):
-40°C to +85°C
DESCRIPTION
The Microchip Technology Inc. 25LC320 is a 32K-bit
serial Electrically Erasable PROM (EEPROM). The
memory is accessed via a simple Serial Peripheral
Interface (SPI) compatible serial bus. The bus signals
required are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
There are two other inputs that provide the end user
with additional flexibility. Communication to the device
can be paused via the hold pin (HOLD). While the
device is paused, transitions on its inputs will be
ignored, with exception of chip select, allowing the host
to service higher priority interrupts. Also write opera-
tions to the Status Register can be disabled via the
write protect pin (WP).
PACKAGE TYPES
DIP/SOIC
CS 1
SO 2
WP 3
VSS 4
TSSOP
CS 1
SO 2
NC 3
NC 4
NC 5
WP 6
VSS 7
BLOCK DIAGRAM
Status
Register
8 VCC
7 HOLD
6 SCK
5 SI
14 VCC
13 HOLD
12 NC
11 NC
10 NC
9 SCK
8 SI
HV Generator
I/O Control
Logic
Memory
Control
Logic
X
Dec
EEPROM
Array
Page Latches
WP
SI
SO
CS
SCK
HOLD
Vcc
Vss
Y Decoder
Sense Amp.
R/W Control
SPI is a trademark of Motorola.
© 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS21158B-page 1
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25LC320
2.0 PRINCIPLES OF OPERATION
The 25LC320 is a 4096 byte EEPROM designed to
interface directly with the serial peripheral interface
(SPI™) port of many of today’s popular microcontroller
families, including Microchip’s midrange PIC16CXX
microcontrollers. It may also interface with microcontrol-
lers that do not have a built-in SPI™ port by using dis-
crete I/O lines programmed properly with software.
The 25LC320 contains an 8-bit instruction register. The
part is accessed via the SI pin, with data being clocked
in on the rising edge of SCK. If the WPEN bit in the Sta-
tus Register is set, the WP pin must be held high to
allow writing to the non-volatile bits in the status regis-
ter.
Table 2-1 contains a list of the possible instruction bytes
and format for device operation. All instructions,
addresses and data are transferred MSB first, LSB last.
Data is sampled on the first rising edge of SCK after CS
goes low. If the clock line is shared with other peripheral
devices on the SPI™ bus, the user can assert the
HOLD input and place the 25LC320 in ‘HOLD’ mode.
After releasing the HOLD pin, operation will resume
from the point when the HOLD was asserted.
2.1 Write Enable (WREN) and Write
Disable (WRDI)
The 25LC320 contains a write enable latch. This latch
must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch. The following is
a list of conditions under which the write enable latch
will be reset:
• Power-up
• WRDI instruction successfully executed
• WRSR instruction successfully executed
• WRITE instruction successfully executed
2.2 Read Status Register (RDSR)
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
7 654 3 2 1 0
WPEN X X X BP1 BP0 WEL WIP
The Write-In-Process (WIP) bit indicates whether the
25LC320 is busy with a write operation. When set to a
‘1’ a write is in progress, when set to a ‘0’ no write is in
progress. This bit is read only.
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘1’ the latch
allows writes to the array and status register, when set
to a ‘0’ the latch prohibits writes to the array and status
register. The state of this bit can always be updated via
the WREN or WRDI commands regardless of the state
of write protection on the status register. This bit is read
only.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write protected. These bits
are set by the user issuing the WRSR instruction.
These bits are non-volatile.
The Write Protect Enable (WPEN) bit is a non-volatile
bit that is available as an enable bit for the WP pin. The
Write Protect (WP) pin and the Write Protect Enable
(WPEN) bit in the status register control the
programmable hardware write protect feature.
Hardware write protection is enabled when WP pin is
low and the WPEN bit is high. Hardware write
protection is disabled when either the WP pin is high or
the WPEN bit is low. When the chip is hardware write
protected, only writes to non-volatile bits in the status
register are disabled. See Table 2-2 for matrix of
functionality on the WPEN bit and Figure 2-1 for a
flowchart of Table 2-2. See Figure 3-5 for RDSR timing
sequence.
TABLE 2-1: INSTRUCTION SET
Instruction Name Instruction Format
Description
WREN
WRDI
RDSR
WRSR
READ
WRITE
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Set the write enable latch (enable write operations)
Reset the write enable latch (disable write operations)
Read status register
Write status register (write protect enable and block write protection bits)
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
TABLE 2-2: WRITE PROTECT FUNCTIONALITY MATRIX
WPEN
0
0
1
1
X
X
WP
X
X
Low
Low
High
High
WEL
0
1
0
1
0
1
Protected Blocks
Protected
Protected
Protected
Protected
Protected
Protected
Unprotected Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Status Register
Protected
Writable
Protected
Protected
Protected
Writable
© 1996 Microchip Technology Inc.
Preliminary
DS21158B-page 5
Preview 5 Page |
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| Information | Total 12 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ 24LC320-IST.PDF Datasheet ] | |
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