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PDF 24LC41 Data sheet ( Hoja de datos )
| Número de pieza | 24LC41 | |
| Descripción | 1K/4K2.5VDualMode/DualPortI2CSerialEEPROM | |
| Fabricantes | MicrochipTechnology | |
| Logotipo |  |
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24LC41
1K/4K 2.5V Dual Mode, Dual Port I2C™ Serial EEPROM
FEATURES
• Single supply with operation down to 2.5V
• Completely implements DDC1™/DDC2™ interface
for monitor identification
• Separate high speed 2-wire bus for
microcontroller access to 4K-bit Serial EEPROM
• Low power CMOS technology
• 2 mA active current typical
• 20 µA standby current typical at 5.5V
• Dual 2-wire serial interface bus
• Hardware write-protect for both ports
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes (DDC port) or
16 bytes (4K Port)
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• 1,000,000 erase/write cycles guaranteed
• Data retention > 40 years
• 8-pin PDIP package
• Available for extended temperature ranges
- Commercial (C):
0°C to +70°C
- Industrial (I):
-40°C to +85°C
DESCRIPTION
The Microchip Technology Inc. 24LC41 is a dual-port
128 x 8 and 512 x 8-bit Electrically Erasable PROM
(EEPROM). This device is designed for use in applica-
tions requiring storage and serial transmission of con-
figuration and control information. Three modes of
operation have been implemented:
• Transmit-Only Mode for the DDC Monitor Port
• Bi-directional Mode for the DDC Monitor Port
• Bi-directional, industry-standard 2-wire bus for the
4K Microcontroller Access Port
Upon power-up, the DDC Monitor Port will be in the
Transmit-Only Mode, repeatedly sending a serial bit
stream of the entire memory array contents, clocked by
the VCLK/DWP pin. A valid high to low transition on the
DSCL pin will cause the device to enter the bi-direc-
tional Mode, with byte-selectable read/write capability
of the memory array. The 4K-bit microcontroller port is
completely independent of the DDC port, therefore, it
can be accessed continuously by a microcontroller
without interrupting DDC transmission activity. The
24LC41 is available in a standard 8-pin PDIP package
in both commercial and industrial temperature ranges.
PACKAGE TYPE
PDIP
DSCL 1
VCLK/DWP 2
VSS 3
MSDA 4
8 DSDA
7 VCC
6 MWP
5 MSCL
BLOCK DIAGRAM
EDID Table
1K Bit
MSDA
MSCL
4K Bit
Serial
EEPROM
DSDA
VCLK/DWP
DSCL
MWP
DDC is a trademark of the Video Electronics Standards Association.
I2C is a trademark of Philips Corporation.
© 1996 Microchip Technology Inc.
This document was created with FrameMaker 4 0 4
DS21140B-page 1
1 page  
2.1.3 BI-DIRECTIONAL MODE
The DDC Monitor Port can be switched into the bi-
directional Mode (Figure 2-3) by applying a valid high to
low transition on the bi-directional Mode Clock (DSCL).
When the device has been switched into the bi-direc-
tional Mode, the VCLK/DWP input is disregarded, with
the exception that a logic high level is required to
enable write capability. This mode supports a 2-wire bi-
directional data transmission protocol. In this protocol,
a device that sends data on the bus is defined to be the
transmitter, and a device that receives data from the
bus is defined to be the receiver. The bus must be con-
trolled by a master device that generates the bi-direc-
tional Mode Clock (DSCL), controls access to the bus
and generates the START and STOP conditions, while
the DDC Monitor Port acts as the slave. Both master
and slave can operate as transmitter or receiver, but the
master device determines which mode is activated.
24LC41
2.2 Microcontroller Access Port
The Microcontroller Access Port supports a bi-direc-
tional 2-wire bus and data transmission protocol. A
device that sends data onto the bus is defined as trans-
mitter, and a device receiving data as receiver. The bus
has to be controlled by a master device which gener-
ates the serial clock (MSCL), controls the bus access,
and generates the START and STOP conditions, while
the Microcontroller Access Port works as slave. Both
master and slave can operate as transmitter or receiver,
but the master device determines which mode is acti-
vated.
FIGURE 2-3: MODE TRANSITION
DSCL
Transmit Only Mode
Bi-Directional Mode
TVHZ
DSDA
VCLK/DWP
© 1996 Microchip Technology Inc.
DS21140B-page 5
5 Page 
8.0 PIN DESCRIPTIONS
8.1 DSDA
This pin is used to transfer addresses and data into and
out of the DDC Monitor Port, when the device is in the
bi-directional Mode. In the Transmit-Only Mode, which
only allows data to be read from the device, data is also
transferred on the DSDA pin. This pin is an open drain
terminal, therefore the DSDA bus requires a pullup
resistor to VCC (typical 10KΩ for 100 kHz, 1KΩ for 400
kHz).
For normal data transfer in the bi-directional Mode,
DSDA is allowed to change only during DSCL or MSDA
low. Changes during DSCL high are reserved for indi-
cating the START and STOP conditions.
8.2 DSCL
This pin is the clock input for the DDC Monitor Port
while in the bi-directional Mode, and is used to synchro-
nize data transfer to and from the device. It is also used
as the signaling input to switch the device from the
Transmit-Only Mode to the bi-directional Mode. It must
remain high for the chip to continue operation in the
Transmit-Only Mode.
8.3 VCLK/DWP
This pin is the clock input for the DDC Monitor Port
while in the Transmit-Only Mode. In the Transmit-Only
Mode, each bit is clocked out on the rising edge of this
signal. In the bi-directional Mode, a high logic level is
required on this pin to enable write capability.
24LC41
8.4 MSCL
This pin is the clock input for the Microcontroller Access
Port, and is used to synchronize data transfer to and
from the device.
8.5 MSDA
This pin is used to transfer addresses and data into and
out of the Microcontroller Access Port. This pin is an
open drain terminal, therefore the MSDA bus requires
a pullup resistor to VCC (typical 10KΩ for 100 kHz, 1KΩ
for 400 kHz).
MSDA is allowed to change only during MSCL low.
Changes during MSCL high are reserved for indicating
the START and STOP conditions.
8.6 MWP
This pin is used to write protect the 4K memory array
for the Microcontroller Access Port.
This pin must be connected to either VSS or VCC.
If tied to Vss, normal memory operation is enabled
(read/write the entire memory).
If tied to VCC, WRITE operations are inhibited. The
entire memory will be write-protected. Read operations
are not affected.
© 1996 Microchip Technology Inc.
DS21140B-page 11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet 24LC41.PDF ] | |
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