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24LC515 데이터시트 PDF




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부품번호 24LC515 기능
기능 512KI2CCMOSSerialEEPROM
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24LC515 데이터시트, 핀배열, 회로
24AA515/24LC515/24FC515
512K I2CCMOS Serial EEPROM
Device Selection Table
Part
Number
VCC
Range
24AA515 1.8-5.5V
24LC515 2.5-5.5V
24FC515 2.5-5.5V
100 kHz for VCC < 2.5V.
Max Clock
Frequency
400 kHz
400 kHz
1 MHz
Temp
Ranges
I
I
I
Features
• Low-power CMOS technology
- Maximum write current 3 mA at 5.5V
- Maximum read current 400 µA at 5.5V
- Standby current 100 nA typical at 5.5V
• 2-wire serial interface bus, I2Ccompatible
• Cascadable for up to four devices
• Self-timed ERASE/WRITE cycle
• 64-byte Page Write mode available
• 5 ms max write cycle time
• Hardware write-protect for entire array
• Output slope control to eliminate ground bounce
• Schmitt Trigger inputs for noise suppression
• 100,000 erase/write cycles
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP, SOIC packages
• Temperature ranges:
- Industrial (I):
-40°C to +85°C
Description
The Microchip Technology Inc. 24AA515/24LC515/
24FC515 (24XX515*) is a 64K x 8 (512K bit) Serial
Electrically Erasable PROM, capable of operation
across a broad voltage range (1.8V to 5.5V). It has
been developed for advanced, low power applications
such as personal communications or data acquisition.
This device has both byte write and page write capabil-
ity of up to 64 bytes of data. This device is capable of
both random and sequential reads. Reads may be
sequential within address boundaries 0000h to 7FFFh
& 8000h to FFFFh. Functional address lines allow up to
four devices on the same data bus. This allows for up
to 2 Mbits total system EEPROM memory. This device
is available in the standard 8-pin plastic DIP and SOIC
packages.
Package Type
PDIP
A0 1
A1 2
A2 3
VSS 4
SOIC
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
8 VCC
7 WP
6 SCL
5 SDA
Block Diagram
A0 A1 WP
HV Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
I/O
SCL
SDA
VCC
VSS
EEPROM
Array
Page Latches
YDEC
Sense AMP
R/W Control
24XX515 is used in this document as a generic part number
for the 24AA515/24LC515/24FC515 devices.
2003 Microchip Technology Inc.
Preliminary
DS21673C-page 1




24LC515 pdf, 반도체, 판매, 대치품
24AA515/24LC515/24FC515
FIGURE 1-1:
BUS TIMING DATA
SCL
SDA
IN
SDA
OUT
5
7
6
16
3
2
8
9
13
(protected)
WP
(unprotected)
D4
4
10
14
11 12
DS21673C-page 4
Preliminary
2003 Microchip Technology Inc.

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24LC515 전자부품, 판매, 대치품
24AA515/24LC515/24FC515
5.0 DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a 4-bit control code; for the
24XX515, this is set as ‘1010’ binary for read and write
operations. The next bit of the control byte is the block
select bit (B0). This bit acts as the A15 address bit for
accessing the entire array. The next two bits of the
control byte are the Chip Select bits (A1, A0). The Chip
Select bits allow the use of up to four 24XX515 devices
on the same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
correspond to the logic levels on the corresponding A1
and A0 pins for the device to respond. These bits are in
effect the two Most Significant bits of the word address.
The last bit of the control byte defines the operation to
be performed. When set to a one, a read operation is
selected, and when set to a zero, a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). Because
only A14…A0 are used, the upper address bit is a don’t
care. The upper address bits are transferred first,
followed by the less significant bits.
Following the Start condition, the 24XX515 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a ‘1010’ code and appro-
priate device select bits, the slave device outputs an
Acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24XX515 will select a read or
write operation.
This device has an internal addressing boundary
limitation that is divided into two segments of 256K bits.
Block select bit ‘B0’ is used in place of address bit
location ‘A15’ to control access to each segment.
FIGURE 5-1:
CONTROL BYTE
FORMAT
Read/Write Bit
Control Code
Chip Select
Bits
S 1 0 1 0 B0 A1 A0 R/W ACK
Start Bit
Slave Address
Acknowledge Bit
5.1 Contiguous Addressing Across
Multiple Devices
The Chip Select bits A1, A0 can be used to expand the
contiguous address space for up to 2 Mbit by adding up
to four 24XX515's on the same bus. In this case,
software can use A0 of the control byte as address bit
A16 and A1 as address bit A17. It is not possible to
sequentially read across device boundaries.
Each device has internal addressing boundary
limitations. This divides each part into two segments of
256K bits. The block select bit ‘B0’ controls access to
each “half” rather than address bit location A15.
Sequential read operations are limited to 256K blocks.
To read through four devices on the same bus, eight
random Read commands must be given.
FIGURE 5-2:
ADDRESS SEQUENCE BIT ASSIGNMENTS
CONTROL BYTE
ADDRESS HIGH BYTE
ADDRESS LOW BYTE
1
0
1
0
B
0
A
1
A
0
R/W
CONTROL BLOCK CHIP
CODE SELECT SELECT
BIT BITS
X
A A AA A
14 13 12 11 10
A
9
A
8
A
7
A
0
X = Don’t Care Bit
2003 Microchip Technology Inc.
Preliminary
DS21673C-page 7

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