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기능 2K2.5VI2CSerialEEPROMwithSoftwareWriteProtect
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24LC52-ISN 데이터시트, 핀배열, 회로
24LCS52
2K 2.5V I2CSerial EEPROM with Software Write Protect
FEATURES
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current typical
- 10 µA standby current typical at 5.5V
- 5 µA standby current typical at 3.0V
• Organized as a single block of 256 bytes (256 x 8)
• Software write protection for lower 128 bytes
• Hardware write protection for entire array
• 2-wire serial interface bus, I2Ccompatible
• 100kHz (2.5V) and 400kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 3.5 ms typical write cycle time for page-write
• 10,000,000 erase/write cycles guaranteed
• ESD protection >4,000V
• Data retention > 200 years
• 8-pin DIP, SOIC or TSSOP packages
• Available for extended temperature ranges
- Commercial (C):
0°C to +70°C
- Industrial (I):
-40°C to +85°C
DESCRIPTION
The Microchip Technology Inc. 24LCS52 is a 2K bit
Electrically Erasable PROM capable of operation
across a broad voltage range (2.5V to 5.5V). This
device has a software write protect feature for the lower
half of the array, as well as an external pin that can be
used to write protect the entire array. The software write
protect feature is enabled by sending the device a spe-
cial command, and once this feature has been enabled,
it cannot be reversed. In addition to the software pro-
tect feature, there is a WP pin that can be used to write
protect the entire array, regardless of whether the soft-
ware write protect register has been written or not. This
allows the system designer to protect none, half or all of
the array, depending on the application. The device is
organized as a single block of 256 x 8-bit memory with
a 2-wire serial interface. Low voltage design permits
operation down to 2.5 volts with typical standby and
active currents of only 5 µA and 1 mA respectively. The
device has a page-write capability for up to 16 bytes of
data. The device is available in the standard 8-pin DIP,
8-pin SOIC and TSSOP packages.
PACKAGE TYPES
PDIP/SOIC
A0 1
A1 2
A2 3
Vss 4
8 Vcc
7 WP
6 SCL
5 SDA
TSSOP
A0 1
A1 2
A2 3
Vss 4
8 Vcc
7 WP
6 SCL
5 SDA
BLOCK DIAGRAM
A0 A1 A2
WP
I/O
Control
Logic
Memory
Control
Logic
XDEC
SDA SCL
Vcc
Vss
HV Generator
Software write
protected area
(00h-7Fh)
Standard
Array
Write Protect
Circuitry
YDEC
SENSE AMP
R/W CONTROL
I2C is a trademark of Philips Corporation.
© 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS21166B-page 1




24LC52-ISN pdf, 반도체, 판매, 대치품
24LCS52
2.0 FUNCTIONAL DESCRIPTION
The 24LCS52 supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24LCS52
works as slave. Both master and slave can operate as
transmitter or receiver but the master device deter-
mines which mode is activated.
3.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1 Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2 Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3 Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4 Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last six-
teen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.
3.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note:
The 24LCS52 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition.
3.6 Device Addressing
A control byte is the first byte received following the
START condition from the master device. The first part
of the control byte consists of a 4-bit control code which
is set to 1010 for normal read and write operations and
0110 for writing to the write protect register. The control
byte is followed by three chip select bits (A2, A1, A0).
The chip select bits allow the use of up to eight
24LCS52 devices on the same bus and are used to
determine which device is accessed. The chip select
bits in the control byte must correspond to the logic lev-
els on the corresponding A2, A1 and A0 pins for the
device to respond. The device will not acknowledge if
you attempt a read command with the control code set
to 0110.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
SCL (A) (B) (C) (D)
(C) (A)
SDA
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
DS21166B-page 4
Preliminary
© 1996 Microchip Technology Inc.

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24LC52-ISN 전자부품, 판매, 대치품
24LCS52
7.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
7.1 Current Address Read
The 24LCS52 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n, the next current address read
operation would access data from address n + 1. Upon
receipt of the slave address with the R/W bit set to one,
the 24LCS52 issues an acknowledge and transmits the
eight bit data word. The master will not acknowledge
the transfer but does generate a stop condition and the
24LCS52 discontinues transmission (Figure 7-1).
7.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LCS52 as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24LCS52 will then
issue an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24LCS52 dis-
continues transmission (Figure 7-2). After this com-
mand, the internal address counter will point to the
address location following the one that was just read.
7.3 Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24LCS52 transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24LCS52 to transmit the next sequentially
addressed 8-bit word (Figure 7-3).
To provide sequential reads the 24LCS52 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
FIGURE 7-1:
CURRENT ADDRESS READ
BUS ACTIVITY
MASTER
SDA LINE
S
T
A
R
T
S
BUS ACTIVITY
CONTROL
BYTE
A
C
K
DATA
S
T
O
P
P
N
O
A
C
K
FIGURE 7-2: RANDOM READ
BUS ACTIVITY
MASTER
S
T
A
R
T
CONTROL
BYTE
SDA LINE
S
BUS ACTIVITY
WORD
ADDRESS (n)
A
C
K
S
T
A
R
T
S
A
C
K
CONTROL
BYTE
A
C
K
DATA (n)
FIGURE 7-3: SEQUENTIAL READ
S
T
O
P
P
N
O
A
C
K
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
CONTROL
BYTE
A
C
K
DATA n
DATA n + 1
DATA n + 2
AAA
CCC
KKK
DATA n + X
S
T
O
P
P
N
O
A
C
K
© 1996 Microchip Technology Inc.
Preliminary
DS21166B-page 7

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