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부품번호 24LC61-P 기능
기능 1K/2KSoftwareAddressableI2CSerialEEPROM
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24LC61-P 데이터시트, 핀배열, 회로
M 24LCS61/24LCS62
1K/2K Software Addressable I2CSerial EEPROM
PRODUCT OFFERING
Device
24LCS61
24LCS62
Array
Size
Voltage
Range
1K bits 2.5V-5.5V
2K bits 2.5V-5.5V
Software
Write
Protection
Entire Array
Lower Half
FEATURES
• Low power CMOS technology
- 1 mA active current typical
- 10 µA standby current typical at 5.5V
• Software addressability allows up to 255 devices
on the same bus
• 2-wire serial interface bus, I2C compatible
• Automatic bus arbitration
• Wakes up to control code 0110
• General purpose output pin can be used to
enable other circuitry
• 100 kHz and 400 kHz compatibility
• Page-write buffer for up to 16 bytes
• 10 ms max write cycle time for byte or page write
• 10,000,000 erase/write cycles guaranteed
• 8-pin PDIP, SOIC or TSSOP packages
• Temperature ranges supported:
- Commercial (C):
- Industrial (I):
0°C to +70°C
-40°C to +85°C
DESCRIPTION
The Microchip Technology Inc. 24LCS61/62 is a 1K/2K
bit Serial EEPROM developed for applications that
require many devices on the same bus but do not have
the I/O pins required to address each one individually.
These devices contain an 8 bit address register that is
set upon power-up and allows the connection of up to
255 devices on the same bus. When the process of
assigning ID values to each device is in progress, the
device will automatically handle bus arbitration if more
than one device is operating on the bus. In addition, an
external open drain output pin is available that can be
used to enable other circuitry associated with each
individual system. Low current design permits opera-
tion with typical standby and active currents of only
10 µA and 1 mA respectively. The device has a page-
write capability for up to 16 bytes of data. The device is
available in the standard 8-pin PDIP, SOIC (150 mil),
and TSSOP packages.
PACKAGE TYPES
PDIP
NC 1
NC
EDS
2
3
Vss 4
8 Vcc
7 NC
6 SCL
5 SDA
SOIC
NC
NC
EDS
Vss
1
2
3
4
TSSOP
NC
NC
EDS
VSS
1
2
3
4
8
VCC
7 NC
6 SCL
5 SDA
8 Vcc
7 NC
6 SCL
5 SDA
BLOCK DIAGRAM
EDS
HV Generator
I/O
Control
Logic
SDA SCL
Vcc
Vss
Memory
Control
Logic
XDEC
EEPROM
Array
ID Register
Serial Number
YDEC
SENSE AMP
R/W CONTROL
I2C is a trademark of Philips Corporation.
© 1997 Microchip Technology Inc.
Preliminary
DS21226A-page 1




24LC61-P pdf, 반도체, 판매, 대치품
24LCS61/62
2.0 PIN DESCRIPTIONS
2.1 SDA (Serial Data)
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to VCC (typical 10 kfor 100 kHz, 2 kfor
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions. The SDA pin has Schmitt trigger and filter circuits
which suppress noise spikes to assure proper device
operation even on a noisy bus
2.2 SCL (Serial Clock)
This input is used to synchronize the data transfer from
and to the device. The SCL pin has Schmitt trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
2.3 EDS (External Device Select)
The External Device Select (EDS) pin is an open drain
output that is controlled by using the OE bit in the con-
trol byte. It can be used to enable other circuitry when
the device is selected. A pull-up resistor must be added
to this pin for proper operation. This pin should not be
pulled up to a voltage higher than Vcc+1V. See
Section 9.0 for more details.
3.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1 Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2 Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3 Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4 Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
data bytes transferred between the START and STOP
conditions is determined by the master device and is
theoretically unlimited, although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL (A) (B) (D) (D)
(C) (A)
SDA
START
CONDITION
DATA OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
DS21226A-page 4
Preliminary
© 1997 Microchip Technology Inc.

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24LC61-P 전자부품, 판매, 대치품
24LCS61/62
5.0 ASSIGNING THE ID BYTE
The 24LCS61/62 device contains a special register
which holds an 8-bit ID byte that is used as an address
to communicate with a specific device on the bus. All
read and write commands to the device must include
this ID address byte. Upon power-up, the ID byte will
default to 00h. Communicating with the device using
the default address is typically done only at testing or
programming time and not when it is connected to a
bus with more than one device. Before the device can
be used on a common bus with other devices, a unique
ID byte address must be assigned to every device.
5.1 Assign Address Command
The ID byte is assigned by sending the Assign Address
command. This command queries any device con-
nected to the bus and utilizing the automatic bus arbi-
tration feature, assigns an ID byte to the device that
remains on the bus after arbitration is complete. Once
a device has been assigned an ID byte, it will no longer
respond to Assign Address commands until power is
cycled or the Clear Address command is sent. The
Assign Address command must be repeated for each
device on the bus until all devices have been assigned
an ID byte.
The format for the Assign Address command is shown
in Figure 5-1. The command consists of the control
byte, the ID byte to be assigned to the device remaining
when the arbitration is complete, and 48 bits of data
being transmitted by devices on the bus. If the OE bit is
set to a 1, then any device who has not been assigned
an address will assert their respective EDS pin after the
acknowledge bit following the Device ID byte. After the
control byte and ID byte are sent, each device will begin
to transmit its unique 48-bit serial number. The
24LCS61/62 must acknowledge the control byte and
the device ID byte, and the master must acknowledge
each byte of the serial number transmitted by the
device. As each bit is clocked out, each device will
monitor the bus to detect if another device is also trans-
mitting. If any device is outputting a logic ‘1’ on the bus
and it detects that the bus is at a logic ‘0’, then it
assumes that another device is controlling the bus. As
soon as any device detects that it is not controlling the
bus it will immediately stop transmitting data and return
to standby mode. The master must end the command
by sending a no ack after all 6 bytes of the serial num-
ber have been transmitted, followed by a Stop bit.
Sending the Stop bit in any other position of the com-
mand will result in the command aborting and all
devices releasing the bus with no address assigned. If
a device transmits its entire 48 bit serial number without
releasing the bus to another device, then the ID byte
transmitted within the command is transferred to the
internal ID byte register upon receipt of the Stop bit and
it will now respond only to commands that contain this
ID byte (or the Clear Address command). Once a
device has been assigned an ID byte, it will no longer
respond to Assign Address commands until power is
cycled or the Clear Address command is sent.
This process of assigning ID bytes is repeated by the
controller until no more devices respond to the Assign
Address command. At this point, all devices on the bus
have been assigned an ID byte and standard read and
write commands can be executed to each individual
device.
The ID byte is stored in a volatile SRAM register, and if
power is removed from the device or the Clear Address
command is sent, then the ID byte will default to
address 00 and the process of assigning an ID value
must be repeated.
FIGURE 5-1: ASSIGN ADDRESS COMMAND
A unique address must be assigned to each
device on the bus
STOP bit must occur here
or command will abort
S
T
A CONTROL
R BYTE
T
Device ID Byte
6 Bytes (48 Bits) of Device Serial Number
with each byte separated by an ack bit
S
0
1
1
0
O
E
1
0
0
A AAA
C CCC
K KKK
S
T
O
P
P
N
O
A
C
K
© 1997 Microchip Technology Inc.
Preliminary
DS21226A-page 7

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