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PDF 24LC65-IP Data sheet ( Hoja de datos )
| Número de pieza | 24LC65-IP | |
| Descripción | 64K 2.5V I2C Smart Serial EEPROM | |
| Fabricantes | MicrochipTechnology | |
| Logotipo |  |
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24LC65
64K 2.5V I2C™ Smart Serial™ EEPROM
FEATURES
• Voltage operating range: 2.5V to 6.0V
- Peak write current 3 mA at 6.0V
- Maximum read current 150 µA at 6.0V
- Standby current 1 µA typical
• Industry standard two wire bus protocol I2C™
compatible
• 8 byte page, or byte modes available
• 2 ms typical write cycle time, byte or page
• 64-byte input cache for fast write loads
• Up to 8 devices may be connected to the same
bus for up to 512K bits total memory
• Including 100 kHz (2.5V) and 400 kHz (5.0V)
compatibility
• Programmable block security options
• Programmable endurance options
• Schmitt trigger, filtered inputs for noise suppres-
sion
• Output slope control to eliminate ground bounce
• Self-timed ERASE and WRITE cycles
• Power on/off data protection circuitry
• Endurance:
- 10,000,000 E/W cycles guaranteed for a High
Endurance Block
- 1,000,000 E/W cycles guaranteed for a Stan-
dard Endurance Block
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP/SOIC packages
• Temperature ranges
- Commercial (C):
0°C to +70°C
- Industrial (I)
-40°C to +85°C
DESCRIPTION
The Microchip Technology Inc. 24LC65 is a “smart” 8K
x 8 Serial Electrically Erasable PROM. This device
has been developed for advanced, low power applica-
tions such as personal communications, and provides
the systems designer with flexibility through the use of
many new user-programmable features. The 24LC65
offers a relocatable 4K bit block of ultra-high-endurance
memory for data that changes frequently. The remain-
der of the array, or 60K bits, is rated at 1,000,000
ERASE/WRITE (E/W) cycles guaranteed. The 24LC65
features an input cache for fast write loads with a
capacity of eight pages, or 64 bytes. This device also
features programmable security options for E/W protec-
tion of critical data and/or code of up to fifteen 4K
I2C is a trademark of Philips Corporation.
Smart Serial is a trademark of Microchip Technology Inc.
PACKAGE TYPES
PDIP
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 NC
6 SCL
5 SDA
SOIC
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 NC
6 SCL
5 SDA
BLOCK DIAGRAM
A0..A2
HV Generator
I/O
Control
Logic
I/O SCL
SDA
Vcc
Vss
Memory
Control
Logic
XDEC
EEPROM ARRAY
Page Latches
Cache
YDEC
Sense AMP
R/W Control
blocks. Functional address lines allow the connection of
up to eight 24LC65's on the same bus for up to 512K
bits contiguous EEPROM memory. Advanced CMOS
technology makes this device ideal for low-power non-
volatile code and data applications. The 24LC65 is
available in the standard 8-pin plastic DIP and 8-pin
surface mount SOIC package.
© 1996 Microchip Technology Inc.
DS21073E-page 1
This document was created with FrameMaker 4 0 4
1 page  
24LC65
3.6 Device Addressing
A control byte is the first byte received following the
start condition from the master device. The control byte
consists of a four bit control code, for the 24LC65 this is
set as 1010 binary for read and write operations. The
next three bits of the control byte are the device select
bits (A2, A1, A0). They are used by the master device
to select which of the eight devices are to be accessed.
These bits are in effect the three most significant bits of
the word address. The last bit of the control byte defines
the operation to be performed. When set to a one a
read operation is selected, when set to a zero a write
operation is selected. The next two bytes received
define the address of the first data byte (Figure 4-1).
Because only A12..A0 are used, the upper three
address bits must be zeros. The most significant bit of
the most significant byte is transferred first. Following
the start condition, the 24LC65 monitors the SDA bus
checking the device type identifier being transmitted.
Upon receiving a 1010 code and appropriate device
select bits, the slave device (24LC65) outputs an
acknowledge signal on the SDA line. Depending upon
the state of the R/W bit, the 24LC65 will select a read
or write operation.
Operation Control Code Device Select R/W
Read
Write
1010
1010
Device Address
Device Address
1
0
FIGURE 3-2:
START
CONTROL BYTE
ALLOCATION
READ/WRITE
SLAVE ADDRESS
R/W A
1 0 1 0 A2 A1 A0
4.0 WRITE OPERATION
4.1 Byte Write
Following the start condition from the master, the con-
trol code (four bits), the device select (three bits), and
the R/W bit which is a logic low is placed onto the bus
by the master transmitter. This indicates to the
addressed slave receiver (24LC65) that a byte with a
word address will follow after it has generated an
acknowledge bit during the ninth clock cycle. Therefore
the next byte transmitted by the master is the high-order
byte of the word address and will be written into the
address pointer of the 24LC65. The next byte is the
least significant address byte. After receiving another
acknowledge signal from the 24LC65 the master device
will transmit the data word to be written into the
addressed memory location. The 24LC65 acknowl-
edges again and the master generates a stop condi-
tion. This initiates the internal write cycle, and during
this time the 24LC65 will not generate acknowledge
signals (Figure 4-1).
4.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LC65 in the same way as
in a byte write. But instead of generating a stop condi-
tion the master transmits up to eight pages of eight data
bytes each (64 bytes total) which are temporarily stored
in the on-chip page cache of the 24LC65. They will be
written from the cache into the EEPROM array after the
master has transmitted a stop condition. After the
receipt of each word, the six lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remain con-
stant. If the master should transmit more than eight
bytes prior to generating the stop condition (writing
across a page boundary), the address counter (lower
three bits) will roll over and the pointer will be incre-
mented to point to the next line in the cache. This can
continue to occur up to eight times or until the cache is
full, at which time a stop condition should be generated
by the master. If a stop condition is not received, the
cache pointer will roll over to the first line (byte 0) of the
cache, and any further data received will overwrite pre-
viously captured data. The stop condition can be sent
at any time during the transfer. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin. The 64 byte cache will con-
tinue to capture data until a stop condition occurs or the
operation is aborted (Figure 4-2).
FIGURE 4-1:
BUS ACTIVITY
MASTER
BYTE WRITE
S
T
A
R
CONTROL
BYTE
T
SDA LINE
S
BUS ACTIVITY
WORD
ADDRESS
00 0
A
C
K
A
C
K
DATA
S
T
O
P
P
A
C
K
© 1996 Microchip Technology Inc.
DS21073E-page 5
5 Page 
24LC65
FIGURE 8-2: CACHE WRITE TO THE ARRAY STARTING AT A PAGE BOUNDARY
1 Write command initiated at byte 0 of page 3 in the array;
First data byte is loaded into the cache byte 0.
2 64 bytes of data are loaded into cache.
cache page 0
cache cache
byte 0 byte 1
•••
cache cache page 1 cache page 2
byte 7 bytes 8-15 bytes 16-23
•••
cache page 7
bytes 56-63
3 Write from cache into array initiated by STOP bit.
Page 0 of cache written to page 3 of array.
Write cycle is executed after every page is written.
4 Remaining pages in cache are written
to sequential pages in array.
page 0 page 1 page 2 byte 0 byte 1 • • • byte 7 page 4 • • • page 7 array row n
page 0 page 1 page 2
page 3
page 4 • • • page 7 array row n + 1
5 Last page in cache written to page 2 in next row.
FIGURE 8-3: CACHE WRITE TO THE ARRAY STARTING AT A NON-PAGE BOUNDARY
Last 2 bytes
loaded into
page 0 of cache.
3
cache
byte 0
1 Write command initiated; 64 bytes of data
2 Last 2 bytes loaded 'roll over'
loaded into cache starting at byte 2 of page 0.
to beginning.
cache cache
cache cache page 1 cache page 2
cache page 7
byte 1 byte 2 • • • byte 7 bytes 8-15 bytes 16-23 • • • bytes 56-63
4 Write from cache into array initiated by STOP bit.
Page 0 of cache written to page 3 of array.
5 Remaining bytes in cache are
Write cycle is executed after every page is written. written sequentially to array.
page 0 page 1 page 2 byte 0 byte 1 byte 2 byte 3 byte 4
page 0 page 1 page 2
page 3
6 Last 3 pages in cache written to next row in array.
•••
byte 7 page 4
page 4
•••
•••
page 7
array
row n
page 7
array
row
n+1
© 1996 Microchip Technology Inc.
DS21073E-page 11
11 Page | ||
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| PDF Descargar | [ Datasheet 24LC65-IP.PDF ] | |
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