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N25Q00AA 데이터시트 PDF




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부품번호 N25Q00AA 기능
기능 NOR Flash Memory
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N25Q00AA 데이터시트, 핀배열, 회로
1Gb, 3V, Multiple I/O Serial NOR Flash Memory
Features
Micron Serial NOR Flash Memory
3V, Multiple I/O, 4KB Sector Erase
N25Q00AA
Features
• Stacked device (four 256Mb die)
• SPI-compatible serial bus interface
• Double transfer rate (DTR) mode
• 2.7–3.6V single supply voltage
• 108 MHz (MAX) clock frequency supported for all
protocols in single transfer rate (STR) mode
• 54 MHz (MAX) clock frequency supported for all
protocols in DTR mode
• Dual/quad I/O instruction provides increased
throughput up to 54 MB/s
• Supported protocols
– Extended SPI, dual I/O, and quad I/O
– DTR mode supported on all
• Execute-in-place (XIP) mode for all three protocols
– Configurable via volatile or nonvolatile registers
– Enables memory to work in XIP mode directly af-
ter power-on
• PROGRAM/ERASE SUSPEND operations
• Available protocols
– Available READ operations
– Quad or dual output fast read
– Quad or dual I/O fast read
• Flexible to fit application
– Configurable number of dummy cycles
– Output buffer configurable
• Software reset
• 3-byte and 4-byte addressability mode supported
• 64-byte, user-lockable, one-time programmable
(OTP) dedicated area
• Erase capability
– Subsector erase 4KB uniform granularity blocks
– Sector erase 64KB uniform granularity blocks
– Single die erase (32MB)
• Write protection
– Software write protection applicable to every
64KB sector via volatile lock bit
– Hardware write protection: protected area size
defined by five nonvolatile bits (BP0, BP1, BP2,
BP3, and TB)
– Additional smart protections, available upon re-
quest
• Electronic signature
– JEDEC-standard 2-byte signature (BA21h)
– Unique ID code (UID): 17 read-only bytes,
including: Two additional extended device ID
bytes to identify device factory options; and cus-
tomized factory data (14 bytes)
• Minimum 100,000 ERASE cycles per sector
• More than 20 years data retention
• Packages – JEDEC-standard, all RoHS-compliant
– L-PBGA-24b05/6mm x 8mm ( also known as
LBGA24 )
– SOP2-16/300 mils (also known as SO16W, SO16-
Wide, SOIC-16 )
PDF: 09005aef8480cede
n25q_1gb_3V_65nm.pdf - Rev. M 03/14 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
http://www.Datasheet4U.com




N25Q00AA pdf, 반도체, 판매, 대치품
1Gb, 3V, Multiple I/O Serial NOR Flash Memory
Features
List of Figures
Figure 1: Logic Diagram ................................................................................................................................... 7
Figure 2: 24-Ball LBGA (Balls Down) ................................................................................................................. 8
Figure 3: 16-Pin, Plastic Small Outline — SO16 (Top View) ................................................................................ 8
Figure 4: Block Diagram ................................................................................................................................ 11
Figure 5: Bus Master and Memory Devices on the SPI Bus ............................................................................... 17
Figure 6: SPI Modes ....................................................................................................................................... 17
Figure 7: Internal Configuration Register ........................................................................................................ 19
Figure 8: Upper and Lower Memory Array Segments ....................................................................................... 24
Figure 9: READ REGISTER Command ............................................................................................................ 32
Figure 10: WRITE REGISTER Command ......................................................................................................... 34
Figure 11: READ LOCK REGISTER Command ................................................................................................. 36
Figure 12: WRITE LOCK REGISTER Command ............................................................................................... 37
Figure 13: READ ID and MULTIPLE I/O Read ID Commands .......................................................................... 39
Figure 14: READ Command ........................................................................................................................... 46
Figure 15: FAST READ Command ................................................................................................................... 46
Figure 16: DUAL OUTPUT FAST READ Command .......................................................................................... 47
Figure 17: DUAL INPUT/OUTPUT FAST READ Command .............................................................................. 47
Figure 18: QUAD OUTPUT FAST READ Command ......................................................................................... 48
Figure 19: QUAD INPUT/OUTPUT FAST READ Command ............................................................................. 48
Figure 20: FAST READ Command – DTR ......................................................................................................... 50
Figure 21: DUAL OUTPUT FAST READ Command – DTR ................................................................................ 51
Figure 22: DUAL INPUT/OUTPUT FAST READ Command – DTR .................................................................... 51
Figure 23: QUAD OUTPUT FAST READ Command – DTR ............................................................................... 52
Figure 24: QUAD INPUT/OUTPUT FAST READ Command – DTR ................................................................... 52
Figure 25: PAGE PROGRAM Command .......................................................................................................... 55
Figure 26: DUAL INPUT FAST PROGRAM Command ...................................................................................... 56
Figure 27: EXTENDED DUAL INPUT FAST PROGRAM Command ................................................................... 56
Figure 28: QUAD INPUT FAST PROGRAM Command ..................................................................................... 57
Figure 29: EXTENDED QUAD INPUT FAST PROGRAM Command ................................................................... 58
Figure 30: WRITE ENABLE and WRITE DISABLE Command Sequence ............................................................ 60
Figure 31: SUBSECTOR and SECTOR ERASE Command .................................................................................. 62
Figure 32: DIE ERASE Command ................................................................................................................... 63
Figure 33: RESET ENABLE and RESET MEMORY Command ........................................................................... 66
Figure 34: READ OTP Command .................................................................................................................... 67
Figure 35: PROGRAM OTP Command ............................................................................................................ 68
Figure 36: XIP Mode Directly After Power-On .................................................................................................. 71
Figure 37: Power-Up Timing .......................................................................................................................... 73
Figure 38: Reset AC Timing During PROGRAM or ERASE Cycle ........................................................................ 76
Figure 39: Reset Enable ................................................................................................................................. 76
Figure 40: Serial Input Timing ........................................................................................................................ 76
Figure 41: Hold Timing .................................................................................................................................. 77
Figure 42: Output Timing .............................................................................................................................. 77
Figure 43: VPPH Timing .................................................................................................................................. 78
Figure 44: AC Timing Input/Output Reference Levels ...................................................................................... 80
Figure 45: L-PBGA-24b05/6mm x 8mm .......................................................................................................... 84
Figure 46: SOP2-16/300 mils .......................................................................................................................... 85
PDF: 09005aef8480cede
n25q_1gb_3V_65nm.pdf - Rev. M 03/14 EN
4 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.

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N25Q00AA 전자부품, 판매, 대치품
1Gb, 3V, Multiple I/O Serial NOR Flash Memory
Device Description
XIP Mode
XIP mode requires only an address (no instruction) to output data, improving random
access time and eliminating the need to shadow code onto RAM for fast execution.
All protocols support XIP operation. For flexibility, multiple XIP entry and exit methods
are available. For applications that must enter XIP mode immediately after power-up,
nonvolatile configuration register bit settings can enable XIP as the default mode.
Device Configurability
The N25Q family offers additional features that are configured through the nonvolatile
configuration register for default and/or nonvolatile settings. Volatile settings can be
configured through the volatile and volatile-enhanced configuration registers. These
configurable features include the following:
• Number of dummy cycles for the fast READ commands
• Output buffer impedance
• SPI protocol types (extended SPI, DIO-SPI, or QIO-SPI)
• Required XIP mode
• Enabling/disabling HOLD (RESET function)
• Enabling/disabling wrap mode
Figure 1: Logic Diagram
VCC
DQ0
C
S#
VPP/W#/DQ2
HOLD#/DQ3
NOR die 4
NOR die 3
NOR die 2
DQ1
NOR die 1
VSS
Note: 1. Reset functionality is available in devices with a dedicated part number. See Part Num-
ber Ordering Information for more details.
PDF: 09005aef8480cede
n25q_1gb_3V_65nm.pdf - Rev. M 03/14 EN
7 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.

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부품번호상세설명 및 기능제조사
N25Q00AA

NOR Flash Memory

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