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24WC128 데이터시트 PDF




CatalystSemiconductor에서 제조한 전자 부품 24WC128은 전자 산업 및 응용 분야에서
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부품번호 24WC128 기능
기능 128K-Bit I2C Serial CMOS E2PROM
제조업체 CatalystSemiconductor
로고 CatalystSemiconductor 로고


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24WC128 데이터시트, 핀배열, 회로
Preliminary
CAT24WC128
128K-Bit I2C Serial CMOS E2PROM
FEATURES
s 1MHz I2C Bus Compatible*
s 1.8 to 6 Volt Operation
s Low Power CMOS Technology
s 64-Byte Page Write Buffer
s Self-Timed Write Cycle with Auto-Clear
s Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT24WC128 is a 128K-bit Serial CMOS E2PROM
internally organized as 16384 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements. The
s Write Protect Feature
– Entire Array Protected When WP at VIH
s 100,000 Program/Erase Cycles
s 100 Year Data Retention
s 8-Pin DIP, 8-Pin SOIC or 14-pin TSSOP
CAT24WC128 features a 64-byte page write buffer. The
device operates via the I2C bus serial interface and is
available in 8-pin DIP, 8-pin SOIC or 14-pin TSSOP
packages.
PIN CONFIGURATION
DIP Package (P)
NC
NC
NC
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
SOIC Package (J,K)
NC
NC
NC
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
TSSOP Package (U14)
NC 1 14 VCC
NC 2 13 WP
NC 3 12 NC
NC 4 11 NC
NC 5 10 NC
NC 6 9 SCL
VSS 7 8 SDA
24WC128 F01
PIN FUNCTIONS
Pin Name
Function
SDA
Serial Data/Address
SCL Serial Clock
WP Write Protect
VCC +1.8V to +6V Power Supply
VSS Ground
BLOCK DIAGRAM
EXTERNAL LOAD
VCC
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
SDA
START/STOP
LOGIC
XDEC
CONTROL
WP LOGIC
SCL STATE COUNTERS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
512
E2PROM
256 256X512
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
24WC128 F02
© 1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25060-00 6/99 S-1




24WC128 pdf, 반도체, 판매, 대치품
CAT24WC128
Preliminary
PIN DESCRIPTIONS
SCL: Serial Clock
The serial clock input clocks all data transferred into or
out of the device.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with
other open drain or open collector outputs.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to Vcc, the
entire memory is write protected. When left floating,
memory is unprotected.
I2C BUS PROTOCOL
The features of the I2C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC128 monitors
the SDA and SCL lines and will not respond until this
condition is met.
Figure 1. Bus Timing
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
tF tHIGH tR
tLOW
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
SDA IN
SDA OUT
tAA tDH
tSU:STO
tBUF
5020 FHD F03
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
Figure 3. Start/Stop Timing
SDA
SCL
Doc. No. 25060-00 6/99 S-1
START BIT
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
5020 FHD F04
STOP BIT
4
5020 FHD F05

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24WC128 전자부품, 판매, 대치품
Preliminary
CAT24WC128
READ operation. The Master device first performs a
dummywrite operation by sending the START condi-
tion, slave address and byte addresses of the location it
wishes to read. After CAT24WC128 acknowledges, the
Master device sends the START condition and the slave
address again, this time with the R/W bit set to one. The
CAT24WC128 then responds with its acknowledge and
sends the 8-bit byte requested. The master device does
not send an acknowledge but will generate a STOP
condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24WC128 sends the initial 8-
bit byte requested, the Master will respond with an
acknowledge which tells the device it requires more
Figure 8. Immediate Address Read Timing
data. The CAT24WC128 will continue to output an 8-bit
byte for each acknowledge sent by the Master. The
operation will terminate when the Master fails to re-
spond with an acknowledge, thus sending the STOP
condition.
The data being transmitted from CAT24WC128 is out-
putted sequentially with data from address N followed
by data from address N+1. The READ operation ad-
dress counter increments all of the CAT24WC128 ad-
dress bits so that the entire memory array can be read
during one operation. If more than E (where E=16383)
bytes are read out, the counter will wrap aroundand
continue to clock out data bytes.
BUS ACTIVITY:
MASTER
S
T
A
R
T
SDA LINE S
SLAVE
ADDRESS
A
C
K
DATA
S
T
O
P
P
N
O
A
C
K
SCL 8 9
SDA
8TH BIT
DATA OUT
NO ACK
STOP
24WC128 F10
Figure 9. Selective Read Timing
BUS ACTIVITY:
MASTER
S
T
A
R
T
SDA LINE S
SLAVE
ADDRESS
BYTE ADDRESS
A15A8
A7A0
**
A
C
K
A
C
K
*=Don't Care Bit
7
S
T
A SLAVE
R ADDRESS
T
S
A
C
K
A
C
K
DATA
S
T
O
P
P
N
O
A
C
K
24WC128 F11
Doc. No. 25060-00 6/99 S-1

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부품번호상세설명 및 기능제조사
24WC128

128K-Bit I2C Serial CMOS E2PROM

CatalystSemiconductor
CatalystSemiconductor

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