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PDF RP506Kxx1B Data sheet ( Hoja de datos )
| Número de pieza | RP506Kxx1B | |
| Descripción | PWM/VFM Step-down DC/ DC Converter | |
| Fabricantes | RICOH | |
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RP506K Series
2A*1 PWM/VFM Step-down DC/ DC Converter with Synchronous Rectifier
NO.EA-296-120525
OUTLINE
The RP506K Series are low supply current CMOS-based PWM/VFM step-down DC/ DC converters with
synchronous rectifier featuring 2A*1 output current. Internally, a single IC consists of an oscillator, a reference
voltage unit, an error amplifier, a switching control circuit, a mode control circuit, a soft start circuit, a latch
protection circuit, an under-voltage lockout (UVLO) circuit, a thermal shutdown circuit, and switching transistors.
By simply using an inductor and capacitors as external components, without connecting any diode, a low ripple
and high efficiency synchronous rectifier step-down DC/ DC converter can be easily configured.
RP506K is available in DFN(PLP)2527-10 package which achieves high-density mounting on boards. RP506K
is available in the fixed output voltage type (RP506Kxx1A/ B/ D/ E) which can be set by 0.1 V step and the output
voltage accuracy is as high as ±1.5% or ±18mV, or the adjustable output voltage type (RP506K001C/ F) which
can be set by using the external resistors.
The oscillator frequency can be selected from 2.25MHz (RP506Kxx1A/ B/ C) or 1.2MHz (RP506K001C/ F). By
inputting a signal to MODE pin, RP506K can choose PWM/VFM auto switching control or forced PWM control. In
low output current, PWM/VFM auto switching control automatically switches from PWM mode to VFM mode in
order to achieve high efficiency. Likewise, in low output current, fixed PWM control switches at fixed frequency in
order to reduce noise.
RP506K contains a latch type protection circuit which latches the built-in driver to the OFF state during high
load or if the output is short-circuited for a specified time (protection delay time). The latch protection circuit can
be released by once setting the IC into the standby mode with the CE pin and then setting it back to the active
mode, or, by turning the power off and back on. Setting the supply voltage lower than the UVLO detector
threshold can also release the latch protection circuit. RP506K also contains a thermal shutdown circuit which
detects overheating of the regulator if the output pin (VOUT) is shorted to the ground pin (GND) etc. and stops
regulator operation to protect it from damage.
The soft-start time is fixed within the IC (Typ. 150µs), but it is also adjustable by using external capacitors.
RP506K includes a power good (PG) function which monitors the VOUT pin voltage or the fee dback pin vol tage
(VFB), and switches the PG pin to low if any abnormal condition is detected.
*1 This is an approximate value. The output current depends on conditions and external components.
1
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1 page  
PIN CONFIGURATION
Top View
10 9 8 7
6
RP506K
Bottom View
12345
12345
10 9 8 7 6
PIN DESCRIPTION
RP506K: DFN(PLP)2527-10*7
Pin No.
Symbol
Description
1
PVIN
PVIN Input Voltage Pin*8
2
AVIN
AVIN Input Voltage Pin*8
3 PG Power Good Pin
4 CE Chip Enable Pin (“H” active)
5
MODE
Mode Control Pin
(“H” Forced PWM Control, “L” PWM/ VFM Auto Switching Control)
6 TSS Soft-start Pin
7
VOUT/ VFB
Output/ Feedback Voltage Pin
8
AGND
Analog Ground Pin*9
9 LX Switching Pin
10
PGND
Power Ground Pin*9
*7 The tab on the bottom of the package enhances thermal performance and is electrically connected to GND
(substarate level). It is recommended that the tab be connected to the ground plane on the board. If not, the tab can
be left open.
*8 No.1 pin and No.2 pin must be wired to the VIN plane when mounting on boards.
*9 No.8 pin and No.10 pin must wired to the GND plane when mounting on boards.
5
5 Page 
RP506K
SOFT START TIME ADJUSTABLE FUNCTION AND POWER GOOD FUNCTION
Soft-start Time Adjustable Function
Soft-start time (tstart) of RP506K Series is adjustable by connecting a soft-start time adjustable capacitor (CSS)
between the TSS pin and GND. tstart can be set from Typ. 0.15ms. As the diagram below shows, if 0.1µF CSS is
connected, tstart will be 30ms. The TSS pin must be open if the soft-start time function is not used. tstart is set to
0.15ms (Typ.) when the TSS pin is open.
tstart
30ms
15ms
3ms
0.15ms
0 470pF 0.01μF
0.047μF
CSS vs. tstart (Typ.)
0.1μF CSS
Power Good Function
RP506K Series contains a power good function using Nch open drain. If any a bnormal condition is detected,
the power g ood function turns Nch tra nsistor on and switches the PG pin to low . If the ca use of the a bnormal
condition is removed, the power good function turns Nch transistor off and switches the P G pin b ack to high.
After the recovery from abnormal condition, it t akes typi cally 0.1ms fo r the I C to turns Nch tran sistor off. The
followings are the abnormal conditions that the power good function can detect.
・CE=”L” (Shut down) ・UVLO (Shut down) ・Thermal Shutdown
・Over Voltage Detection: Typ . VSET x 1.2V (RP506Kxx1A/ B/ D/ E) or 0.72V (RP506K001C/ F)
・Under Voltage Detection: Typ . VSET x 0.8V (RP506Kxx1A/ B/ D/ E) or 0.48V (RP506K001C/ F)
When using the power good function, the resistance of PG pin (RPG) should be between 10kΩ to 100kΩ. The
PG pin must be open or connected to GND if the power good function is not used.
11
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| Páginas | Total 43 Páginas | |
| PDF Descargar | [ Datasheet RP506Kxx1B.PDF ] | |
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