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74S175 데이터시트 PDF




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부품번호 74S175 기능
기능 Hex/Quad D Flip-Flop
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74S175 데이터시트, 핀배열, 회로
August 1986
Revised April 2000
DM74S174 • DM74S175
Hex/Quad D Flip-Flop with Clear
General Description
These positive-edge-triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop lo gic. All h ave a d irect cle ar
input, and the quad (DM74S175) versions feature comple-
mentary outputs from each flip-flop.
Information at the D inputs meeting the setup time require-
ments is transferred to the Q outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a partic-
ular voltage level and is not directly related to the transition
time of the positive-going pulse. When the clock input is at
either th e H IGH or LOW l evel, th e D i nput si gnal has no
effect at the output.
Features
s DM74S174 contain six flip-flops with single-rail outputs.
s DM74S175 con tain fo ur fl ip-flops w ith do uble-rail out-
puts.
s Buffered clock and direct clear inputs
s Individual data input to each flip-flop
s Applications include:
Buffer/storage registers
Shift registers
Pattern generators
s Typical clock frequency 110 MHz
s Typical power dissipation per flip-flop 75mW
Ordering Code:
Order Number
DM74S174N
DM74S175N
Package Number
Package Description
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagrams
DM74S174
DM74S175
© 2000 Fairchild Semiconductor Corporation DS006472
www.fairchildsemi.com
http://www.Datasheet4U.com




74S175 pdf, 반도체, 판매, 대치품
Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Typ
Min Max
(Note 5)
Units
VI Input Clamp Voltage
VOH HIGH Level
Output Voltage
VOL LOW Level
Output Voltage
II Input Current @ Max Input Voltage
IIH HIGH Level Input Current
IIL LOW Level Input Current
IOS Short Circuit Output Current
ICC Supply Current (DM74S174)
ICC Supply Current (DM74S175)
Note 5: All typicals are at VCC = 5V, TA = 25°C.
VCC = Min, II = −18 mA
VCC = Min, IOH = Max
VIL = Max, VIH = Min
VCC = Min, IOL = Max
VIH = Min, VIL = Max
VCC = Max, VI = 5.5V
VCC = Max, VI = 2.7V
VCC = Max, VI = 0.5V
VCC = Max (Note 6)
VCC = Max (Note 7)
VCC = Max (Note 7)
1.2 V
2.7 3.4
V
0.5 V
1 mA
50 µA
2m
A
40
100
mA
90 144 mA
60 96 mA
Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 7: With all outputs OPEN and 4.5V applied to all DATA and CLEAR inputs, ICC is measured after a momentary ground, then 4.5V applied to the CLOCK
input.
Switching Characteristics
at VCC = 5V and TA = 25°C
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
Parameter
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output (DM74S175 Only)
Propagation Delay Time
HIGH-to-LOW Level Output
From (Input)
To (Output)
Clock to Output
Clock to Output
Clear to Q
Clear to Q
RL = 280
CL = 15 pF
CL = 50 pF
Min Max Min Max
75 65
12 15
17 21
15 18
22 23
Units
MHz
ns
ns
ns
ns
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부품번호상세설명 및 기능제조사
74S175

Hex/Quad D Flip-Flop

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