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PDF AND9071D Data sheet ( Hoja de datos )
| Número de pieza | AND9071D | |
| Descripción | Noise Management in Motor Drives | |
| Fabricantes | ON Semiconductor | |
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AND9071/D
Noise Management in Motor
Drives with IGBTs
http://onsemi.com
APPLICATION NOTE
INTRODUCTION
The introduction of IGBT s has enabled motor drives to
move to higher switching frequencies and hence, more
compact implementations. However, a side product of these
advances is the increased vulnerability to the EMI/noise
issues. The EMI/EMC management has always been
a challenging aspect of any motor drive design and
development, with a significant amount of time spent in
finding empirical solutions to problems that manifest
themselves during the development. The introduction of
IGBTs switching at higher frequencies may complicate this
task due to (a) higher switching frequencies and (b)
increased proximity between components/subsystems
offered by the higher level of compactness.
However, as many practicing engineers recognize,
techniques exist to address EMI issues ef
fectively.
A number of these techniques are discussed in this section.
The focus is on building preventive solutions into the design
and layout rather than dealing with them through debugging
and redesign.
A typical block diagram of the motor drive circuit is
shown in Figure 1 and will be used to illustrate various
techniques for EMI management.
IGBT based
Inverter
AC Input
Front-end SMPS
(ac-dc converter)
DC Link
Motor
Digital Controller
(uC, DSP or
other)
IGBT
Drivers
Sensors
Figure 1. Typical Motor Drive System Block Diagram
© Semiconductor Components Industries, LLC, 2014
February, 2014 − Rev. 1
1
Publication Order Number:
AND9071/D
http://www.Datasheet4U.com
1 page  
AND9071/D
In a motor drive, layout is a critical part of the total design.
Often, getting a system to work properly is actually more
a matter of layout than circuit design. The following
discussion covers some general layout principals, power
stage layouts, and controller layouts. It is realized by
practicing engineers that there is no single “correct” layout
for an application. A good layout generally involves making
a number of on the spot technical trade-of
fs that
cumulatively lead to better system performance.
General Principles:
There are several general layout principles that are
important to motor drive design. They can be described as
five rules:
Rule 1: Minimize Loop Areas. A loop is the circuit trace path
from the source of a signal (e.g. driver , FB node) to its
destination (e.g. IGBT, error amp) and back to its source
through the return path. This is a general principle that
applies to both power stages and noise sensitive inputs.
Loops are antennas. At noise sensitive inputs, the area
enclosed by an incoming signal path and its return is
proportional to the amount of noise picked up by the input.
At power stage outputs, the amount of noise that is radiated
is also proportional to loop area. A corollary of this rule is
that the placement of key components that are connected is
very critical and they should be placed as close to each other
as possible.
Rule 2: Cancel fields by running equal currents that flow in
opposite directions as close as possible to each other. If two
equal currents flow in opposite directions, the resulting
electromagnetic fields will cancel as the two currents are
brought infinitely close together . In printed circuit board
layout, this situation can be approximated by running signals
and their returns along the same path but on different layers.
Field cancellation is not perfect due to the finite physical
separation, but is suf ficient to warrant serious attention in
motor drive layouts. Looked at from a different perspective,
this is another way of looking at Rule 1, i.e. minimize loop
areas.
Rule 3: On traces that carry high speed signals avoid 90
degree angles, including “T” connections. If you think of
high speed signals in terms of wavefronts moving down a
trace, the reason for avoiding 90 degree angles is
straightforward. To a high speed wavefront, a 90 degree
angle is a discontinuity that produces unwanted reflections.
From a practical point of view, 90 degree turns on a single
trace are easy to avoid by using two 45 degree angles or a
curve. Where two traces come together to form a “T”
connection, adding some copper pour to cut across the right
angles accomplishes the same thing.
Rule 4: Connect signal circuit grounds to power grounds at
only one point. The reason for this constraint is that transient
voltage drops along power grounds can be substantial, due
to high values of di/dt flowing through finite inductance. If
signal processing circuit returns are connected to power
ground a multiple points, then these transients will show up
as return voltage differences at different points in the signal
processing circuitry. Since signal processing circuitry
seldom has the noise immunity to handle power ground
transients, it is generally necessary to tie the signal ground
to the power ground at only one point. This rule can also be
extended to use of ground planes. For power circuits, it is
important to have either separate ground planes or ensure
that the high current path on the ground plane does not
traverse through sensitive signal ground areas on the same
plane.
Rule 5: Use Vias very sparingly and selectively. Although
vias offer an easy routing solution for complex/dense pcbs,
injudicious use of them could lead to EMI and other
problems. Vias are used primarily for 3 purposes:
1. To provide signal connection to/from an inner
layer plane such as ground plane as well as to
provide signal connection between components
places on separate layers.
2. To provide alternative routing path for a trace
when routing is not possible on the same layer due
to presence of other higher priority traces.
3. To provide thermal relief for high current carrying
paths/planes on the inner layers.
However, insertion of vias reduces the area of a plane or
copper pour , adds capacitance between the vias and the
adjoining signals on all layers and causes diversion in traces
which could have been more directly routed. Thus, addition
of vias involves trade-offs that can be made by experienced
layout designers and circuit designers together during the
layout.
Layout Consideration for Power Stage:
There are two overriding objectives with regard to power
stage layout. First, it is necessary to control noise at the gate
drives so power devices are not turned on when they are
supposed to be of f or vice versa. Second, it is highly
desirable to minimize radiated noise with layout, where tight
loops and field cancellation can reduce the cost of filters and
enclosures. Looking first at the gate drive,
noise
management is greatly facilitated by using the source or
emitter connection for each power device as a miniature
ground plane for that device’s gate drive. This is particularly
important for high side N-Channel gate drives, where the
gate drivers have high dv/dt displacements with respect to
power ground. If the power device’ s source or emitter
connection is used like a ground plane, parasitic capacitive
coupling back to power ground is minimized, thereby
increasing the dv/dt immunity of the gate drive.
To illustrate this point, let’s refer to and assume that the
high-side phase output swings 300 V in 100 nsec as a result
of a switching transition, and that the parasitic capacitance
to power ground, Cp, is only 1 pF. Then a simple i = C(dv/dt)
calculation suggests that 3 mA of charging current will flow
through Cp. This 3 mA into 5.6 kW of node impedance is
much more than enough to cause false transitions. These
numbers illustrate a very high sensitivity to parasitic
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