PDF ATtiny2313A Data sheet ( Hoja de datos )

Número de pieza	ATtiny2313A
Descripción	8-bit Microcontroller
Fabricantes	ATMEL Corporation
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No Preview Available ! Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20 MHz • Data and Non-volatile Program and Data Memories – 2/4K Bytes of In-System Self Programmable Flash • Endurance 10,000 Write/Erase Cycles – 128/256 Bytes In-System Programmable EEPROM • Endurance: 100,000 Write/Erase Cycles – 128/256 Bytes Internal SRAM – Programming Lock for Flash Program and EEPROM Data Security • Peripheral Features – One 8-bit Timer/Counter with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes – Four PWM Channels – On-chip Analog Comparator – Programmable Watchdog Timer with On-chip Oscillator – USI – Universal Serial Interface – Full Duplex USART • Special Microcontroller Features – debugWIRE On-chip Debugging – In-System Programmable via SPI Port – External and Internal Interrupt Sources – Low-power Idle, Power-down, and Standby Modes – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit – Internal Calibrated Oscillator • I/O and Packages – 18 Programmable I/O Lines – 20-pin PDIP, 20-pin SOIC, 20-pad MLF/VQFN • Operating Voltage – 1.8 – 5.5V • Speed Grades – 0 – 4 MHz @ 1.8 – 5.5V – 0 – 10 MHz @ 2.7 – 5.5V – 0 – 20 MHz @ 4.5 – 5.5V • Industrial Temperature Range: -40°C to +85°C • Low Power Consumption – Active Mode • 190 µA at 1.8V and 1MHz – Idle Mode • 24 µA at 1.8V and 1MHz – Power-down Mode • 0.1 µA at 1.8V and +25°C 8-bit Microcontroller with 2/4K Bytes In-System Programmable Flash ATtiny2313A ATtiny4313 Rev. 8246B–AVR–09/11 1 page ATtiny2313A/4313 2. Overview The ATtiny2313A/4313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny2313A/4313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram PA0 - PA2 PORTA DRIVERS VCC GND DATA REGISTER PORTA DATA DIR. REG. PORTA 8-BIT DATA BUS PROGRAM COUNTER PROGRAM FLASH INSTRUCTION REGISTER INSTRUCTION DECODER CONTROL LINES PROGRAMMING LOGIC STACK POINTER SRAM GENERAL PURPOSE REGISTER ALU STATUS REGISTER SPI XTAL1 XTAL2 INTERNAL CALIBRATED OSCILLATOR INTERNAL OSCILLATOR WATCHDOG TIMER MCU CONTROL REGISTER MCU STATUS REGISTER TIMER/ COUNTERS INTERRUPT UNIT EEPROM USI OSCILLATOR TIMING AND CONTROL RESET ON-CHIP DEBUGGER USART 8246B–AVR–09/11 DATA REGISTER PORTB DATA DIR. REG. PORTB PORTB DRIVERS DATA REGISTER PORTD DATA DIR. REG. PORTD PORTD DRIVERS PB0 - PB7 PD0 - PD6 5 5 Page ATtiny2313A/4313 4.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 4-2. AVR CPU General Purpose Working Registers General Purpose Working Registers 70 R0 R1 R2 … R13 R14 R15 R16 R17 … R26 R27 R28 R29 R30 R31 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F X-register Low Byte X-register High Byte Y-register Low Byte Y-register High Byte Z-register Low Byte Z-register High Byte Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 4-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically imple- mented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 4.4.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3. 8246B–AVR–09/11 11 11 Page

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