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PDF AR8228 Data sheet ( Hoja de datos )
| Número de pieza | AR8228 | |
| Descripción | Seven-Port Fast Ethernet Switch | |
| Fabricantes | Atheros | |
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Data Sheet
July 2009
AR8229/AR8228 Seven-Port Fast Ethernet Switch
General Description
The AR8229/AR8228 is a highly integrated
three-Giga MAC plus Five-port Fast Ethernet
switch with non-blocking switch fabric, a high-
performance lookup unit with 1024 MAC
address, 4096 VLAN table, 32 ACL rule table
and a four-traffic class Quality of Service (QoS)
engine. The AR8229/AR8228 has the flexibility
to support various networking applications.
The AR8229/AR8228 support many offload
function to increase the system performance.
The AR8229/AR8228 is designed for cost
sensitive switch applications in wireless AP
router, home gateway, and xDSL/PON/cable
modem platform. The Fast Ethernet in the
AR8229/AR8228 complies fully with IEEE
802.3 standards. The AR8229/AR8228
implements power saving techniques to
facilitate low power consumption. The
AR8229/AR8228 is designed to work in all
environments. True Plug-n-Play is supported
with Auto-Crossover, Auto Polarity, and Auto-
Negotiation in PHYs.
AR8229/AR8228 Features
■ Single-chip seven-port Fast Ethernet QoS
Yswitch
■ Single chip 7 port Fast Ethernet QoS switch
Pcontroller with:
5 port 10/100 UTP + 2 port GMII/RGMII
OMAC
C4 port 10/100 UTP + 2 port GMII/RGMII
MAC + 1 RGMII MAC
T4 port 10/100 UTP + 2 port GMII/RGMII
MAC + 1 port MII PHY
O■ QoS support with four traffic classes based
on arrival port, IEEE802.1p, IPv4 TOS, IPv6
NTC and Destination MAC Address
■ Supports strict priority, WRR, and mix
mode (1 SP + 3 WRR or 2 SP + 2 WRR)
O■ Full IEEE 802.1Q VLAN ID processing per
Dport and VLAN tagging for 4096 VLAN IDs;
■ Autocast MIB counters to cpu port
■ Support ingress & egress rate limit
■ Broadcast storm Suppression
■ Supports port mirror
■ Support MAC and PHY loopback function
for diagnosis
■ Fully compliant with IEEE 802.3/802.3u
auto-negotiation function
■ Flow control fully supported IEEE 802.3x
flow control for full duplex and back
pressure for half duplex
■ Supports port lock function
■ Supports hardware looping detection
■ Power saving on no link and low traffic rate
for 10Base-T
and port based VLANs supported
■ Support VLAN tag insert or remove
function on per-port basis
■ Support QinQ double tag, and 16 entry of
VLAN translation table
■ IGMPv1/v2/v3 and MLDv1/v2 Snooping
with hardware join and fast leave function
■ Support 32 ACL rules and rule based
counters
■ Support 16 PPPoE sessions header remove
■ Port states & BPDU handling support
IEEE802.1D Spanning Tree Protocol
■ High performance lookup engine with 1024
MAC Address with automatic learning and
aging and support for static addresses
■ Support 40 MIB counters per port
© 2009 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Atheros XR®, Driving the Wireless Future®, ROCm®, Super A/G®, Super G®,
Super N®, Total 802.11®, XSPAN®, Wireless Future. Unleashed Now.®, and Wake on Wireless® are registered by Atheros Communications, Inc. Atheros SST™, Signal-
Sustain Technology™, the Air is Cleaner at 5-GHz™, and 5-UP™ are trademarks of Atheros Communications, Inc. The Atheros logo is a registered trademark of Atheros
Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.
COMPANY CONFIDENTIAL
•1
http://www.Datasheet4U.com
1 page  
DATASHEET
1. Pin Descriptions
This section contains a listing of the pin
descriptions (see Table 1-1 on page 10 and
Figure 1-1 on page 6 through Figure 1-4 on
page 9).
The following nomenclature is used for signal
names:
The following nomenclature is used for signal
types described in Table 1-1 on page 10:
D Open drain for digital pads
I Digital input signal
_L At the end of the signal name,
indicates active low signals
I/O Digital bidirectional signal
IA Analog input signal
N_ Near the end of the signal name,
n_ indicates active low signals
IH Digital input with hysteresis
IL Input signals with weak internal
N At the end of the signal name
pull-down, to prevent signals
indicates the negative side of a
from floating when left open
differential signal
NC No connection is made from this
pin to the internal die
YP At the end of the signal name,
Pindicates the positive side of a
DO NOT COdifferentialsignal
O Digital output signal
OA Analog output signal
P A power or ground signal
PD Internal pull-down for digital
input
PU Internal pull-up for digital input
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR8229/AR8228 Seven Port Fast Ethernet Switch • 5
July 2009 • 5
5 Page 
DATASHEET
Table 1-1. Signal to Pin Relationships and Descriptions (continued)
Symbol
Pin Type Description
RXD0_0
RXD1_0
RXD2_0
RXD3_0
RXD4_0
RXD5_0
RXD6_0
RXD7_0
119 I/O, PD GMII/RGMII/MII receive data or configuration; recommend
120 I/O, PD adding a 22 W damping resistor. these are output signals from
121 I/O, PD MAC 0. All the data bits RXD[7:0]_0 are used in GMII mode.
The RXD[3:0]_0 are used as data input when operating at
122 I/O, PD RGMII or MII mode. The reference clock for these output
123 I/O, PD signals will be:
124 I/O, PD
125 I/O, PD 1. RXCLK_0 (pin 117): GMII/RGMII/MII PHY type interface
126
I/O, PU
and MII MAC type interface.
2. TXCLK_0 (pin 128): GMII MAC type interface.
RXDV_0/RXCTR_0
119 I/O, PD GMII/RGMII/MII receive data valid. This is output signal for
MAC0.
TXCLK_0
128
TXEN/TXCTR_0
2
TXD0_0
3
TXD1_0
4
TXD2_0
5
TXD3_0
6
TXD4_0
7
DOTXD5_0
TXD6_0
TXD7_0
MAC 5 RGMII interface
8
9
10
GTXCLK_1/TXCLK_1 80
I/O, PD This pin is the reference clock for TXD[7:0]_0 when operating
NOT COPYI,PD
I, PD
I, PD
I, PD
I, PD
I, PD
I, PD
at MII interface or GMII MAC type interface. The clock will be
output signal at PHY type interface and will be input signal at
MAC type interface.. It also supports 50MHz clock
input(Turbo-MII) when operating in MII mode MAC type
interface.
GMII/RGMII/MII transmit enable, this is input signal for the
MAC0.
GMII/RGMII/MII transmit data, these are input signals for
MAC0. All the data bits TXD[7:0]_0 are used in GMII mode.
The TXD[3:0]_0 are used as data input when operating on
RGMII or MII mode. The reference clock for these input signals
will be:
1. GTXCLK_0 (pin 1): GMII or RGMII PHY type interface or
I, PD
GMII MAC type
2. TXCLK_0 (pin 128): MII mode PHY type interface
I, PD
I/O, PD
GMII/RGMII transmit clock, 125 MHz/25 MHz, or
configuration, recommend to add a 22 Ω damping resistor. This
is the reference clock input for GMII/RGMII mode PHY type
interface or MII mode MAC type interface. It also supports
50MHz clock input(turbo MII) when operating in MII mode
MAC type interface.
RXCLK_1
81 I/O, PD GMII/RGMII receive clock. This is output clock from MAC5 or
PHY4 when AR8229/AR8228 operates at PHY type interface or
GMII mode MAC type interface. It can be 125MHz/25MHz/
2.5MHz depending on the operating speed.
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR8229/AR8228 Seven Port Fast Ethernet Switch • 11
July 2009 • 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AR8228.PDF ] | |
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