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부품번호 ATAES132 기능
기능 32K AES Serial EEPROM
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ATAES132 데이터시트, 핀배열, 회로
ATAES132
32K AES Serial EEPROM Specification
DATASHEET
Features
32Kb Standard Serial EEPROM User Memory
o Compatible with the Atmel® AT24C32D and the Atmel AT2530B
o 16 User Zones of 2Kb Each
High-security features
o AES Algorithm with 128-bit Keys
o AES-CCM for Authentication
o Message Authentication Code for Cryptographic Operations
o Secure Storage for Sixteen 128 bit Keys
o Encrypted User Memory Read and Write
o FIPS Random Number Generator
o 16 High-Endurance Monotonic EEPROM Counters
Flexible User Configured Security
o User Zone Access Rights Independently Configured
o Authentication Prior to Zone Access
Read/Write, Encrypted, or Read-only User Zone Options
High-speed Serial Interface Options
o 10MHz SPI (Mode 0 and 3)
o 1MHz I2C
2.5V to 5.5V Supply, <250nA Sleep
Serial EEPROM Compatible Pinout Packages: SOIC, SOP, or UDFN
Operating Temperature Range: -40°C to +85°C
Description
The Atmel ATAES132 is a high-security, Serial Electrically-Erasable and Programmable
Read-Only Memory (EEPROM) providing both authentication and confidential nonvolatile
data storage capabilities. Access restrictions for the 16 user zones are independently
configured and any key can be used with any zone. Keys can also be used for standalone
authentication. This flexibility permits the ATAES132 to be used in a wide range of
applications.
The AES-128 cryptographic engine operates in AES-CCM mode to provide authentication,
stored data encryption/decryption, and Message Authentication Codes. Data
encryption/decryption can be performed for internally stored data or for small external data
packets, depending upon the configuration. Data encrypted by one ATAES132 device can
be decrypted by another, and vice versa.
Atmel-8760C-CryptoAuth-ATAES132-Datasheet_102013
http://www.Datasheet4U.com




ATAES132 pdf, 반도체, 판매, 대치품
7.18 Lock Command ......................................................................................................................................................... 57
7.19 Nonce Command ...................................................................................................................................................... 59
7.20 NonceCompute Command ........................................................................................................................................ 61
7.21 Random Command ................................................................................................................................................... 63
7.22 Reset Command ....................................................................................................................................................... 65
7.23 Sleep Command........................................................................................................................................................ 66
7.24 WriteCompute Command .......................................................................................................................................... 67
8. Pin Lists ........................................................................................................................................................... 68
8.1 Package Pin List (SOIC and UDFN).......................................................................................................................... 68
8.2 Pin Descriptions ........................................................................................................................................................ 68
9. Electrical Characteristics .................................................................................................................................. 69
9.1 Absolute Maximum Ratings....................................................................................................................................... 69
9.2 Reliability ................................................................................................................................................................... 69
9.3 DC Characteristics..................................................................................................................................................... 70
9.4 AC Characteristics..................................................................................................................................................... 71
Appendix A. Standards and Reference Documents .............................................................................................. 75
A.1 National and International Standards ........................................................................................................................ 75
A.2 References ................................................................................................................................................................ 75
Appendix B. Memory Map ..................................................................................................................................... 76
B.1 Memory Map ............................................................................................................................................................. 76
B.2 EEPROM Page Boundary ......................................................................................................................................... 77
Appendix C. User Memory Map............................................................................................................................. 78
Appendix D. Command Memory Map.................................................................................................................... 79
D.1 Command Memory Buffer ......................................................................................................................................... 79
D.2 Response Memory Buffer.......................................................................................................................................... 80
D.3 IO Address Reset Register........................................................................................................................................ 81
D.4 Device Status Register (STATUS)............................................................................................................................. 81
Appendix E. Configuration Memory Map............................................................................................................... 82
E.1 Configuration Memory Map ....................................................................................................................................... 82
E.2 Configuration Register Descriptions .......................................................................................................................... 84
Appendix F. Key Memory Map .............................................................................................................................. 93
Appendix G. Understanding the STATUS Register ............................................................................................... 94
G.1 Device Status Register (STATUS) Definition............................................................................................................. 94
G.2 STATUS Register Behavior in the I2C Interface Mode .............................................................................................. 96
G.3 STATUS Register Behavior in the SPI Interface Mode............................................................................................ 102
Appendix H. Understanding Counters ................................................................................................................. 108
H.1 Counter Registers.................................................................................................................................................... 108
H.2 Reading the Counter ............................................................................................................................................... 109
H.3 Personalizing the Counters ..................................................................................................................................... 110
Appendix I. Cryptographic Computations........................................................................................................... 111
I.1 MacCount ................................................................................................................................................................ 111
I.2 MacFlag................................................................................................................................................................... 112
I.3 MAC Generation...................................................................................................................................................... 112
I.4 Data Encryption....................................................................................................................................................... 113
I.5 Data Decryption....................................................................................................................................................... 114
I.6 Auth Command MAC............................................................................................................................................... 115
I.7 AuthCheck Command – Auth MAC ......................................................................................................................... 115
4 ATAES132 [Datasheet]
Atmel-8760C-CryptoAuth-ATAES132-Datasheet_102013

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ATAES132 전자부품, 판매, 대치품
1. Introduction
ATAES132 is the first device in a family of high-security Serial EEPROMs using the Advanced Encryption
Standard (AES) cryptographic algorithm. ATAES132 provides 32Kb of EEPROM user data memory, sixteen
128-bit Key Registers, sixteen high-endurance monotonic EEPROM Counters, factory unique Die Identification
Numbers, and a Configuration Memory. The Configuration Memory registers control access to the User Memory,
as well as the restrictions on Key and Counter functionality.
The User Memory can be accessed directly with standard SPI or I2C commands if a user zone is configured for
open or read-only access. If the user zone security is activated, then the extended ATAES132 command set is
used to access the contents of a user zone. The extended ATAES132 commands are executed by writing the
command packet to the virtual memory using standard SPI or I2C Write commands. The response packet is
retrieved by reading it from the virtual memory using standard SPI or I2C Read commands.
The ATAES132 packages are compatible with standard SPI and I2C EEPROM footprints. This allows the
ATAES132 to be inserted into many existing Serial EEPROM applications.
1.1 Scope
This Specification provides all specifications for configuration and operation of the ATAES132.
1.2 Conventions
Table 1-1. Nomenclatures
Nomenclature
Host
Client
Definition
The SPI or I2C Master
Device
The ATAES132 Secure
Serial EEPROM Defined by
this Specification
Notes
The Host initiates all communications with slave devices on the
serial interface bus.
Operates as a SPI or I2C slave.
nnb
Binary Number
Denotes a binary number “nn” (most-significant bit on the left).
0xZZZZ
Hexadecimal Number
Denotes hex number ZZZZ (most-significant bit on the left).
ZZZZh
Hexadecimal Number
Denotes hex number ZZZZ (most-significant bit on the left).
RegName.FieldName
Field Name
RegArray[xx].FieldName Field Name
UZ User Zone
Reference to bit field FieldName in register RegName.
Reference to bit field FieldName in register RegArray[xx],
where xx is the array index.
Reference to a User Zone number.
CntID
Counter ID
Reference to a Counter number.
KeyID
Key ID
Reference to a Key Register number.
ATAES132 [Datasheet]
Atmel-8760C-CryptoAuth-ATAES132-Datasheet_102013
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ATAES132

32K AES Serial EEPROM

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