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DTC34LR86L PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 DTC34LR86L
기능 +3.3V LVDS 24Bit Flat Panel Display (FPD) Receiver
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DTC34LR86L 데이터시트, 핀배열, 회로
DTC34LF8 6L/DTC34LR86L
LVDS Product
DTC34LF86L/DTC34LR86L (Rev. 2.2)
REVISED APR. 2009
+3.3V LVDS 24Bit Flat Panel Display (FPD) Receiver - 85MHz
General Description
The D TC34LF86L/LR86L rec eivers co nvert the L VDS
(Low Voltage Differential Signaling) data streams back
into 28 bit s of CMOS/ TTL dat a with falling edge
(DTC34LF86L) or risin g edge (DTC34LR86L) clock for
convenient int erface with a variet y of L CD p anel
controllers.
A phase-locked transmit clock is transmitte d in p arallel
with the data streams ove r a fif th L VDS link. A
transmitter (DTC34LM85L) w ill inter-o perate w ith a
Falling/Rising edg e rec eiver (DT C34LF86L/LR86L)
without any translation logic.
Using a 8 5 MHz clock, the dat a throu ghputs is 297.5
Mbytes/sec. This chip set is an ide al mean s to solve
EMI and ca ble size problems associat ed with wide,
high speed TTL interfaces.
Features
Wide frequency range : 20 to 85 MHz shift
clock support
Narrow bus (10 lines) reduces cable size
Sing le 3.3V supply
Po wer-Down Mode
Single pixel per clock XGA (1024x768) ready
Supports VGA, SVGA, XGA and SXGA
Up to 297.5 Megabytes/sec bandwidth
Up to 2.38 Gbps throughput
300mV swing LVDS devices for low EMI
PLL requires no external components
Low profile 56-lead TSSOP package (PB Free)
Comp atible with TIA/EIA-644 LVDS standard
Compatible with the National DS90C386,
T hine THC63LVDF84A
Block Diagram
DTC34LF86L/DTC34LR86L
CMOS/TTL OUTPUTS
8
RED
LVDS DATA
( 140 TO 595Mbit/s
On Each LVDS
Channel )
8
GRN
8
BLU
HSYNC
VSYNC
DE(Data Enable)
CNTL
RCLK+/-
(20MHz ~ 85MHz)
PLL CLKOUT
(20MHz ~ 85MHz)
/PDN(Power Down)
-1-
DOESTEK Co., Ltd.
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DTC34LR86L pdf, 반도체, 판매, 대치품
DTC34LF8 6L/DTC34LR86L
AC Timing Diagram
FIGURE 1. Test Pattern “16 Grayscale Test Pattern”
Device Pin Name Signal
CLKOUT Dot CLK
RX0 R0
RX1 R1
RX2 R2
RX3 R3
RX4 R4
RX5 R7
RX6 R5
RX7 G0
RX8 G1
RX9 G2
RX10 G6
RX11 G7
RX12 G3
RX13 G4
RX14 G5
RX15 B0
RX16 B6
RX17 B7
RX18 B1
RX19 B2
RX20 B3
RX21 B4
RX22 B5
RX23 CNTL
RX24 HSYNC
RX25 VSYNC
RX26 DE
RX27 R6
Signal Pattern
FIGURE 2. Test Pattern “Worst Case Pattern”
CLKOUT
T
ODD RX
EVEN RX
FIGURE 3. TTL Output
TTL OUTPUT
TTL OUTPUT LOAD
8pF
80%
TTL OUTPUT
20%
tTLH
-4-
Signal Frequency
f
f/16
f/8
f/4
f/2
Steady State Low
Steady State Low
Steady State Low
Steady State Low
f/16
f/8
f/4
f/2
Steady State Low
Steady State Low
Steady State Low
Steady State Low
f/16
f/8
f/4
f/2
Steady State Low
Steady State Low
Steady State Low
Steady State Low
Steady State High
Steady State High
Steady State High
Steady State High
80%
20%
tTHL
DOESTEK Co., Ltd.

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DTC34LR86L 전자부품, 판매, 대치품
DTC34LF8 6L/DTC34LR86L
FIGURE 9. Package Pin Description
Pin Name
RL0+,RL0-
RL1+, RL1-
RL2+, RL2-
RL3+, RL3-
RCLK+, RCLK-
RX0 ~ RX6
RX7 ~ RX13
RX14 ~ RX20
RX21 ~ RX27
CLKOUT
/PDN
VCC
GND
LVDS VCC
LVDS GND
PLL VCC
PLL GND
Pin #
9, 10
11, 12
15, 16
19, 20
17, 18
27,29,30,32,33,35,37
38,39,43,45,46,47,51
53,54,55,1,3,5,6
7,34,41,42,49,50,2
26
25
31,40,48,56
28,36,44,52
13
8,14,2,1
23
22,24
Type
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
OUT
OUT
OUT
OUT
OUT
IN
Power
Ground
Power
Ground
Power
Ground
Description
LVDS differential data inputs.
LVDS differential clock inputs.
TTL level data outputs.
This includes : 8 Red, 8 Green, 8 Blue, and 4 control lines
(HSYNC, VSYNC, DE, CNTL)
TTL level clock output. This falling edge acts as data strobe
TTL level input. H : Normal operation
L : Power down (all output are low)
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
Power supply for PLL.
Ground pins for PLL.
IMPORTANT NOTICE :
- The contents of this data sheet are subject to change without prior notice.
DOESTEK Co., Ltd. ( www.doestek.co.kr )
6F TechnoComplex Korea Univ., Anam-Dong5-Ga, Songbuk-Gu, SEOUL, KOREA Tel) 82-2-926-9464
- 7 - DOESTEK Co., Ltd.

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부품번호상세설명 및 기능제조사
DTC34LR86L

+3.3V LVDS 24Bit Flat Panel Display (FPD) Receiver

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