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TMP47C101P 데이터시트 PDF




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기능 CMOS 4-Bit Microcontroller
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TMP47C101P 데이터시트, 핀배열, 회로
TOSHIBA
TLCS-47E Series
CMOS 4-bit Microcontroller
TMP47C101P, TMP47C201P,
TMP47C101M, TMP47C201M
TMP47C101/201
The 47C101/201 are high speed and high performance 4-bit sin-
gle chip microcomputers, integrating ROM, RAM, input/output
ports and timer/counters on a chip. The 47C101/201 are the
standard type devices in the TLCS-47E series.
Part No.
TMP47C101P
TMP47C101M
mTMP47C201P
oTMP47C201M
ROM
1024 x 8-bit
2048 x 8-bit
RAM
64 x 4-bit
128 x 4-bit
Package
DIP16
SOP16
DIP16
SOP16
OTP
TMP47P201VP
T.B.D.
TMP47P201VP
T.B.D.
Piggyback + Adapter
TMP47C990E
+ BM1160 (for DIP)
.cFeatures
U• 4-bit single chip microcomputer
t4• Instruction execution time: 1.3µs (at 6MHz)
• Low voltage operation: 2.2V (at 2MHz RC)
• 89 basic instructions
e- Instruction set is the same as TLCS-47 series
e• ROM table look-up instructions
• Subroutine nesting: 15 levels max.
h• 5 interrupt sources (External: 2, Internal: 3)
- All sources have independent latches each, and multiple
Sinterrupt control is available
ta• I/O port (11 pins)
• 12-bit Timer/Counters (TC2)
a- Timer, event counter, and pulse width measurement
mode
• 12-bit programmable Timer (TC1)
.D• Interval Timer
• High current outputs
w- LED direct drive capability: typ. 20mA x 4 bits (Port R4)
• Hold function
w- Battery/Capacitor back-up
w• Real Time Emulator: BM4721A + BM1160 (for DIP)
The information contained here is subject to change without notice.
The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic
equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equip-
ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types
of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
TOSHIBA CORPORATION
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TMP47C101P pdf, 반도체, 판매, 대치품
TMP47C101/201
2. Internal CPU Function
2.1 Program Counter (PC)
The program counter is a 11-bit binary counter which indicates
the address of the program memory storing the next instruc-
tion to be executed.Normally, the PC is incremented by the
number of bytes of the instruction every time it is fetched.
When a branch instruction or a subroutine instruction has been
executed or an interrupt has been accepted, the specified val-
ues listed in Table 2-1 are set to the PC. The PC is initialized to
“0” during reset.
Figure 2-1. Configuration of Program Counter
The PC can directly address a 2048-byte address space.
However, with the short branch, the following points must be
considered:
• Short branch instruction [BSS a]
In [BSS a] instruction execution, when the branch con-
dition is satisfied, the value specified in the instruction
is set to the lower 6 bits of the PC.That is, [BSS a]
becomes the in-page branch instruction. When [BSS
a] is stored at the last address of the page, the upper 5
bits of the PC point the next page, so that branch is
made to the next page.
Table 2-1 Status Change of Program Counter
4/32
TOSHIBA CORPORATION

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TMP47C101P 전자부품, 판매, 대치품
TMP47C101/201
2.4 Data Memory (RAM)
(2) Direct addressing mode
The 47C101 has 64 x 4 bits (addresses 00H through 3FH) of
the data memory (RAM), and the 47C201 has 128 x 4 bits
(addresses 00H through 7FH).
The RAM is addressed in one of the three ways (address-
ing modes):
In this mode, an address is directly specified by the 8
bits of the second byte (operand) in the instruction
field.
Example: LD A, 2CH ; AccRAM [2CH]
(1) Register-indirect addressing mode
(3) Zero-page addressing mode
In this mode, a page is specified by the H register and
an address in the page by the L register.
Example: LD A, @HL ; AccRAM [HL]
In this mode, an address in zero-page (addresses 00H
through 0FH) is specified by the lower 4 bits of the sec-
ond byte (operand) in the instruction field.
Example: ST #3, 05H ; RAM [05H]3
Figure 2-5. Addressing Mode
2.4.1 Data Memory Map
Figure 2-6 shows the data memory map. The data memory is
also used for the following special purpose.
ΠStack and Stack Pointer Word (SPW)
 Data Counter (DC)
Ž Count registers of the timer/counters (TC1, TC2)
 Zero-page
TOSHIBA CORPORATION
Figure 2-6. Data Memory Map (47C201)
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관련 데이터시트

부품번호상세설명 및 기능제조사
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(TMP47C101 / TMP47C201) CMOS 4-bit Microcontroller

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CMOS 4-Bit Microcontroller

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