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PDF TMP47C101M Data sheet ( Hoja de datos )
| Número de pieza | TMP47C101M | |
| Descripción | CMOS 4-Bit Microcontroller | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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TOSHIBA
TLCS-47E Series
CMOS 4-bit Microcontroller
TMP47C101P, TMP47C201P,
TMP47C101M, TMP47C201M
TMP47C101/201
The 47C101/201 are high speed and high performance 4-bit sin-
gle chip microcomputers, integrating ROM, RAM, input/output
ports and timer/counters on a chip. The 47C101/201 are the
standard type devices in the TLCS-47E series.
Part No.
TMP47C101P
TMP47C101M
mTMP47C201P
oTMP47C201M
ROM
1024 x 8-bit
2048 x 8-bit
RAM
64 x 4-bit
128 x 4-bit
Package
DIP16
SOP16
DIP16
SOP16
OTP
TMP47P201VP
T.B.D.
TMP47P201VP
T.B.D.
Piggyback + Adapter
TMP47C990E
+ BM1160 (for DIP)
.cFeatures
U• 4-bit single chip microcomputer
t4• Instruction execution time: 1.3µs (at 6MHz)
• Low voltage operation: 2.2V (at 2MHz RC)
• 89 basic instructions
e- Instruction set is the same as TLCS-47 series
e• ROM table look-up instructions
• Subroutine nesting: 15 levels max.
h• 5 interrupt sources (External: 2, Internal: 3)
- All sources have independent latches each, and multiple
Sinterrupt control is available
ta• I/O port (11 pins)
• 12-bit Timer/Counters (TC2)
a- Timer, event counter, and pulse width measurement
mode
• 12-bit programmable Timer (TC1)
.D• Interval Timer
• High current outputs
w- LED direct drive capability: typ. 20mA x 4 bits (Port R4)
• Hold function
w- Battery/Capacitor back-up
w• Real Time Emulator: BM4721A + BM1160 (for DIP)
The information contained here is subject to change without notice.
The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic
equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equip-
ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types
of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
TOSHIBA CORPORATION
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1 page  
2.2 Program Memory (ROM)
Programs and fixed data are stored in the program memory.
The instruction to be executed next is read from the address
indicated by the contents of the PC.
The fixed data can be read by using the table look-up in-
structions.
• Table look-up instructions
[LDL A, @DC], [LDH A, @DC+]
The table look-up instructions read the lower and
upper 4 bits of the fixed data stored at the address
TMP47C101/201
specified in the data counter (DC) to place them into
the accumulator. [LDL A, @DC] instruction reads the
lower 4 bits of fixed data, and [LDH A, @DC+] instruc-
tion reads the upper 4 bits.
The DC is a 12-bit register, allowing it to address the
entire program memory space.
Example: When [LDL A, @DC] instruction is executed
with the DC value being 7AOH being 58H,
“8” is stored in the accumulator; when [LDH
A, @DC+] instruction is executed, “5” is
stored in the accumulator and the DC value
is incremented to 7A1H.
Figure 2-2. Configuration of Program Memory
2.2.1 Program Memory Capacity
The 47C101 has 1024 x 8 bits (addresses 000H through 3FFH)
of program memory (mask ROM), the 47C201 has 2048 x 8
bits (addresses 000H through 7FFH).
2.2.2 Program Memory Map
Figure 2-3 shows the program memory map. Address 000H -
086H of the program memory are also used for special pur-
poses. On the 47C101, no physical program memory exists in
the address range 400H through 7FFH. However, if this space
is accessed by program, the most significant bit of each
address is always regarded as “0” and the contents of the pro-
gram memory corresponding to the address is always
regarded as “0” and the contents of the program memory cor-
responding to the address 000H through 3FFH are read.
TOSHIBA CORPORATION
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5 Page 
TMP47C101/201
(2) Zero detect information (Z)
This information is “1” when the operation result or the
data to be transferred to the accumulator/data mem-
ory is “0000B”.
2.6 Flags
There is a carry flag (CF), a zero flag (ZF), a status flag (SF), and
a general flag (GF), each consisting of 1 bit. These flags are set
or cleared according to the condition specified by an instruc-
tion. When an interrupt is accepted, the flags are saved on the
stack along with the program counter. When the [RETI]
instruction is executed, the flags are restored from the stack to
the states set before interrupt acceptance.
(1) Carry flag (CF)
The carry flag holds the carry information received from
the ALU at the execution of an addition/subtraction
with carry instruction, a compare instruction, or a
rotate instruction. With a carry flag test instruction, the
CF holds the value specified by it.
Figure 2-11. ALU
Example: The carry information and zero detect
information for 4-bit additions and subtrac-
tions.
Operation
4+2=
7+9=
9+9=
Operation
8-1=
2-2=
5-8=
Result
6
0
2
Result
7
0
3 (1101B)
C
0
1
1
C
1
1
0
Z
0
1
0
Z
0
1
0
Addition/subtraction with carry instructions [ADDC A,
@HL], [SUBRC A, @HL]
The CF becomes the input (Cin) to the ALU to hold the
carry information.
Compare instructions [CMPR A, @HL], [CMPR A, #k]
The CF holds the carry information (non-borrow).
Rotate instructions [ROLC A], [RORC A]
The CF is shifted into the accumulator to hold the car-
ry information (the data shifted out from the accumu-
lator).
Carry flag test instructions [TESTP CF], [TEST CF]
With [TESTP CF] instruction, the content of the CF is
transferred to the SF then the CF is set to “1”.
With [TEST CF] instruction, the value obtained by in-
verting the content of the CF is transferred to the SF
then the CF is cleared to “0”.
(2) Zero flag (ZF)
2.5.2 Accumulator (Acc)
The accumulator is a 4-bit register used to hold source data or
results of the operations and data manipulations.
The zero flag holds the zero detect information (Z)
received from the ALU at the execution of an opera-
tional instruction, a rotate instruction, an input instruc-
tion, or a transfer-to-accumulator instruction.
(3) Status flag (SF)
Figure 2-12. Accumulator
Figure 2-13. Flags
TOSHIBA CORPORATION
The status flag provides the branch condition for a
branch instruction. Branch is performed when this flag
is set to “1”. Normally the SF is set to “1”, so that any
branch instruction can be regarded as an uncondi-
tional branch instruction. When a branch instruction is
executed upon set or clear of the SF according to the
condition specified by an instruction, this instruction
becomes a conditional branch instruction. During
reset, the SF is initialized to “1”, other flags are not
affected.
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| PDF Descargar | [ Datasheet TMP47C101M.PDF ] | |
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