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PDF P3P4GF4BLF Data sheet ( Hoja de datos )
| Número de pieza | P3P4GF4BLF | |
| Descripción | 4G Bits Die DDRIII SDRAM | |
| Fabricantes | Deutron Electronics | |
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4G B Die DDRIII SDRAM Specification
P3P4GF4BLF
Deutron Electronics Corp.
8F, 68, Sec. 3, NanKing E. RD., Taipei 104,
Taiwan, R.O.C.
TEL: (886)-2-2517-7768
FAX: (886)-2-2517-4575
1 page  
MIRA 4G Bits DDR3 SDRAM
CONTENTS
Specifications.................................................................................................................................................1
Features.........................................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Pin Configurations .........................................................................................................................................3
Electrical Conditions ......................................................................................................................................6
Absolute Maximum Ratings ......................................................................................................................... 6
Operating Temperature Condition ............................................................................................................... 6
Recommended DC Operating Conditions (TC = 0C to +85C, VDD, VDDQ = 1.5V 0.075V) .................. 7
AC and DC Input Measurement Levels (TC = 0C to +85C, VDD, VDDQ = 1.5V 0.075V)...................... 7
VREF Tolerances ........................................................................................................................................ 9
Input Slew Rate Derating ........................................................................................................................... 10
AC and DC Logic Input Levels for Differential Signals ............................................................................... 16
AC and DC Output Measurement Levels (TC = 0C to +85C, VDD, VDDQ = 1.5V 0.075V) ................. 21
AC Overshoot/Undershoot Specification.................................................................................................... 23
Output Driver Impedance........................................................................................................................... 24
On-Die Termination (ODT) Levels and I-V Characteristics ........................................................................ 26
ODT Timing Definitions.............................................................................................................................. 28
IDD Measurement Conditions (TC = 0C to +85C, VDD, VDDQ = 1.5V 0.075V) .................................. 32
Electrical Specifications...............................................................................................................................45
DC Characteristics 1 (TC = 0C to +85C, VDD, VDDQ = 1.5V 0.075V) ................................................ 45
Pin Capacitance (TC = 25C, VDD, VDDQ = 1.5V 0.075V) .................................................................... 47
Standard Speed Bins ................................................................................................................................. 48
AC Characteristics (TC = 0C to +85C, VDD, VDDQ = 1.5V 0.075V, VSS, VSSQ = 0V)...................... 51
Block Diagram .............................................................................................................................................64
Pin Function.................................................................................................................................................65
Command Operation ...................................................................................................................................67
Command Truth Table ............................................................................................................................... 67
CKE Truth Table ........................................................................................................................................ 71
Simplified State Diagram .............................................................................................................................72
RESET and Initialization Procedure ............................................................................................................73
Power-Up and Initialization Sequence ....................................................................................................... 73
Reset and Initialization with Stable Power ................................................................................................. 74
Programming the Mode Register.................................................................................................................75
Mode Register Set Command Cycle Time (tMRD) .................................................................................... 75
MRS Command to Non-MRS Command Delay (tMOD) ............................................................................ 75
DDR3 SDRAM Mode Register 0 [MR0] ..................................................................................................... 76
DDR3 SDRAM Mode Register 1 [MR1] ..................................................................................................... 77
DDR3 SDRAM Mode Register 2 [MR2] ..................................................................................................... 78
Data Sheet E1801E22 (Ver. 2.2)
4
5 Page 
MIRA 4G Bits DDR3 SDRAM
Input Slew Rate Derating
For all input signals the total tIS, tDS (setup time) and tIH, tDH (hold time) required is calculated by adding the data
sheet tIS (base), tDS (base) and tIH (base), tDH (base) value to the tIS, tDS and tIH, tDH derating value
respectively.
Example: tDS (total setup time) = tDS (base) + tDS.
Setup (tIS, tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF
(DC) and the first crossing of VIH (AC) min. Setup (tIS, tDS) nominal slew rate for a falling signal is defined as the
slew rate between the last crossing of VREF (DC) and the first crossing of VIL (AC) max. If the actual signal is
always earlier than the nominal slew rate line between shaded ‘VREF (DC) to AC region’, use nominal slew rate for
derating value (See the figure of Slew Rate Definition Nominal).
If the actual signal is later than the nominal slew rate line anywhere between shaded ‘VREF (DC) to AC region’, the
slew rate of a tangent line to the actual signal from the AC level to DC level is used for derating value (see the figure
of Slew Rate Definition Tangent).
Hold (tIH, tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VIL (DC) max. and the first crossing of VREF (DC). Hold (tIH, tDH) nominal slew rate for a falling signal is defined
as the slew rate between the last crossing of VIH (DC) min. and the first crossing of VREF (DC). If the actual signal
is always later than the nominal slew rate line between shaded ‘DC level to VREF (DC) region’, use nominal slew
rate for derating value (See the figure of Slew Rate Definition Nominal).
If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘DC to VREF (DC) region’,
the slew rate of a tangent line to the actual signal from the DC level to VREF (DC) level is used for derating value
(see the figure of Slew Rate Definition Tangent).
For a valid transition the input signal has to remain above/below VIH/VIL(AC) for some time tVAC (see the table of
Required time tVAC above VIH(AC) {below VIL(AC)} for valid transition).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached
VIH/IL (AC) at the time of the rising clock transition) a valid input signal is still required to complete the transition and
reach VIH/IL (AC).
For slew rates in between the values listed in the tables below, the derating values may obtained by linear
interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
[Address/Command Setup and Hold Base-Values for 1V/ns]
DDR3-1600
DDR3-1333
DDR3-1066
Unit Reference
tIS(base) AC175
45
65
125 ps VIH/VIL(AC)
tIS(base) AC150
170
190
275
ps VIH/VIL(AC)
tIH(base) DC100
120
140
200
ps VIH/VIL(DC)
Notes: 1. AC/DC referenced for 1V/ns Address/Command slew rate and 2V/ns differential CK, /CK slew rate.
2. The tIS (base) AC150 specifications are adjusted from the tIS(base) AC175 specification by adding an
additional 125ps for DDR3-1066 or 100ps for DDR3-1600/1333 of derating to accommodate for the lower
alternate threshold of 150mV and another 25ps to account for the earlier reference point [(175mV
150mV)/1V/ns]
Data Sheet E1801E22 (Ver. 2.2)
10
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| PDF Descargar | [ Datasheet P3P4GF4BLF.PDF ] | |
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