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PDF SiT9102 Data sheet ( Hoja de datos )

Número de pieza SiT9102
Descripción 1 to 220 MHz High Performance Oscillator
Fabricantes SiTime 
Logotipo SiTime Logotipo



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No Preview Available ! SiT9102 Hoja de datos, Descripción, Manual

SiT9102
LVPECL / HCSL / LVDS / CML
1 to 220 MHz High Performance Oscillator
Features
• Extremely low RMS phase jitter (random)
• <1 ps (typical)
• Wide frequency range
• 1 MHz to 220 MHz
• 220 MHz to 800 MHz refer to SiT9107
• High frequency stability
• ±10 PPM, ±15 PPM, ±20 PPM
• ±25 PPM, ±50 PPM
• Operating voltage
• 1.8, 2.5 or 3.3 V
• Other voltages up to 3.63 V (contact SiTime)
• Operating temperature range
• Industrial, -40 to 85 °C
• Extended Commercial, -20 to 70 °C
• Commercial, 0 to 70 °C
• Small footprint
• 5.0 x 3.2 x 0.75 mm
• 7.0 x 5.0 x 0.90 mm
• Pb-free and RoHS compliant
• For Spread Spectrum see SiT9002
• Ultra-reliable start up and greater immunity from inter
ference
Benefits
• Ultra fast lead time: 2 to 3 weeks
• No crystal or capacitors required
• Eliminates crystal qualification time
• 50% + board saving space
• More cost effective than quartz oscillators, quartz crystals
and clock ICs.
• Completely quartz-free
Applications
• Server
• Router
• RAID controller
• Gigabit Ethernet
• 10 Gigabit Ethernet
• Fiber Channel
• SATA / SAS
• PCI-Express
• Fully Buffered DIMM
• System clock
• Networking and computing
Block Diagram
Pinout
VDD
OUT- OUT+
ST/OE 1
6 VDD
MEMS
Resonator
High Performance
Phase Lock Loop
NC 2
GND 3
5 OUT-
4 OUT+
ST/OE
GND
SiTime Corporation
Rev. 1.52
990 Almanor Avenue
Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised June 23, 2010

1 page




SiT9102 pdf
SiT9102
LVPECL / HCSL / LVDS / CML
1 to 220 MHz High Performance Oscillator
LVPECL, 2.5V ±10%, -40 to 85°C
Symbol Parameter
Fout
Fstab
Output Frequency
Frequency Stability
Condition
Inclusive of initial stability,
operating temp., rated
power supply voltage
change, load change
0 to 70°C
-20 to 70°C
-40 to 85°C
Fage
DC
tR/tF
PHJ
PJ
Aging
Duty Cycle
Output Rise/Fall Time
RMS Phase Jitter (random)
RMS Period Jitter
First year @ 25°C
20% to 80%
Fout = 106.25 MHz @ BW: 637 kHz to10 MHz
Fout = 156.25 MHz @ BW: 1.875 to 20 MHz
Fout = 200 MHz @ BW: 1 to 20 MHz
Fout = 106.25 MHz
Fout = 156.25 MHz
Fout = 200 MHz
Min.
1.0
-10
-15
-20
-25
-50
45
100
Typ.
150
1.6
0.5
0.7
1.8
1.3
1.3
Max.
220
+10
+15
+20
+25
+50
1
55
300
2.3
1.8
1.8
Unit
MHz
PPM
PPM
PPM
PPM
PPM
PPM
%
ps
ps
ps
ps
ps
ps
ps
HCSL, 3.3V ±10%, -40 to 85°C
Symbol Parameter
Fout
Fstab
Output Frequency
Frequency Stability
Condition
Inclusive of initial stability,
operating temp., rated power
supply voltage change, load
change
0 to 70°C
-20 to 70°C
-40 to 85°C
Fage
DC
tR/tF
PHJ
PJ
Aging
Duty Cycle
Output Rise/Fall Time
RMS Phase Jitter (random)
RMS Period Jitter
First year @ 25°C
20% to 80%
Fout = 100 MHz @ BW: 1.5 MHz to 22 MHz
Fout = 200 MHz @ BW: 1.5 MHz to 22 MHz
Fout = 100 MHz
Fout = 200 MHz
Min.
1.0
-10
-15
-20
-25
-50
45
200
Typ.
280
0.8
0.4
1.6
1.5
Max.
220
+10
+15
+20
+25
+50
1
55
375
2.2
1.9
Unit
MHz
PPM
PPM
PPM
PPM
PPM
PPM
%
ps
ps
ps
ps
ps
Rev. 1.52
Page 5 of 13
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5 Page





SiT9102 arduino
SiT9102
LVPECL / HCSL / LVDS / CML
1 to 220 MHz High Performance Oscillator
SiT9102
OUT+
Drive Device
OUT-
Z0 = 50 Ohm
Z0 = 50 Ohm
50 Ohm
50 Ohm
D+
Receiver Device
D-
VDD <VT < 3.63V
Figure 7. CML Single Load Termination
S iT 9 1 0 2
OUT+
Drive Device
OUT-
50 Ohm
A
Z0 = 50 Ohm
A
Z0 = 50 Ohm
50 Ohm
50
Ohm
B
D+
B
D-
50 Ohm
R e c e iv e r
D e v ic e
VDD < VT1 < 3.63V
VDD <VT2 < 3.63V
N o te s:
1. For D C -coupled operation, VT1 = VT2
2. For AC coupled operation, include/insert decoupling caps at points A or B
2. For AC -coupled operation w ith capacitors placed at point A, V T2 sets the input com m on m ode of R eceiver D evice and need
not to be related to VT1
Figure 8. CML Double Load Termination
Rev. 1.52
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