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6N40C 데이터시트 PDF




Fairchild Semiconductor에서 제조한 전자 부품 6N40C은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 6N40C 자료 제공

부품번호 6N40C 기능
기능 FQP6N40C
제조업체 Fairchild Semiconductor
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6N40C 데이터시트, 핀배열, 회로
FQP6N40C
N-Channel QFET® MOSFET
400 V, 6.0 A, 1.0
December 2013
Description
This N-Channel enhancement mode power MOSFET is
produced using Fairchild Semiconductor’s proprietary planar
stripe and DMOS technology. This advanced MOSFET
technology has been especially tailored to reduce on-state
resistance, and to provide superior switching performance
and high avalanche energy strength. These devices are
suitable for switched mode power supplies, active power
factor correction (PFC), and electronic lamp ballasts.
Features
6.0 A, 400 V, RDS(on) = 1.0 (Max.) @ VGS = 10 V,
ID = 3 A
• Low Gate Charge (Typ. 16 nC)
• Low Crss (Typ. 15 pF)
• 100% Avalanche Tested
D
GDS
TO-220
Absolute Maximum Ratings TC = 25°C unless otherwise noted.
Symbol
VDSS
ID
IDM
VGSS
EAS
IAR
EAR
dv/dt
PD
TJ, TSTG
TL
Parameter
Drain-Source Voltage
Drain Current
Drain Current
- Continuous (TC = 25°C)
- Continuous (TC = 100°C)
- Pulsed
Gate-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (TC = 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering,
1/8" from Case for 5 Seconds.
(Note 1)
(Note 2)
(Note 1)
(Note 1)
(Note 3)
G
S
FQP6N40C
400
6
3.6
24
± 30
270
6
7.3
4.5
73
0.58
-55 to +150
300
Thermal Characteristics

+θ 
+θ

Thermal Resistance, Junction-to-Case, Max.
Thermal Resistance, Junction-to-Ambient, Max.
FQP6N40C
1.71
62.5
Unit
V
A
A
A
V
mJ
A
mJ
V/ns
W
W/°C
°C
°C

6?
6?
©2003 Fairchild Semiconductor Corporation
FQP6N40C Rev. C1
1
www.fairchildsemi.com




6N40C pdf, 반도체, 판매, 대치품
Typical Characteristics (Continued)
1.2
1.1
1.0
0.9 Notes :
1.
2.
IVDG=S =2500Vμ
A
0.8
-100
-50 0
50 100 150
T , Junction Temperature [oC]
J
200
Figure 7. Breakdown Voltage Variation
vs Temperature
102
Operation in This Area
is Limited by R DS(on)
10 µs
101 100 µs
1 ms
10 ms
100 ms
100 DC
10-1
10-2
100
Notes :
1. T = 25 oC
C
2. TJ = 150 oC
3. Single Pulse
101 102
VDS, Drain-Source Voltage [V]
103
Figure 9. Maximum Safe Operating Area
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-100
Notes :
1. V = 10 V
GS
2. I = 3 A
D
-50 0
50 100 150
TJ, Junction Temperature [oC]
200
Figure 8. On-Resistance Variation
vs Temperature
6
5
4
3
2
1
0
25 50 75 100 125 150
TC, Case Temperature []
Figure 10. Maximum Drain Current
vs Case Temperature
100 D =0 .5
0 .2
0 .1
1 0-1
0 .0 5
0 .0 2
0 .0 1
1 0-2
1 0 -5
sin g le p u lse
N o tes :
1 . Z θ JC(t) = 1 .7 1 /W M a x.
2 . D uty F ac to r, D = t1/t2
3 . T JM - T C = P DM * Z θ JC(t)
PDM
t1
t2
1 0 -4
1 0 -3
1 0 -2
1 0 -1
100
101
t1 , S q u a r e W a v e P u l s e D u r a t i o n [ s e c ]
Figure 11. Transient Thermal Response Curve
©2003 Fairchild Semiconductor Corporation
FQP6N40C Rev. C1
4
www.fairchildsemi.com

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6N40C 전자부품, 판매, 대치품
Mechanical Dimensions
Figure 16. TO220, Molded, 3-Lead, Jedec Variation AB
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specif-
ically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/package/packageDetails.html?id=PN_TO220-003
©2003 Fairchild Semiconductor Corporation
FQP6N40C Rev. C1
7
www.fairchildsemi.com

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