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PDF HD74ALVCH16820 Data sheet ( Hoja de datos )

Número de pieza HD74ALVCH16820
Descripción 3.3-V 10-bit Flip Flops with Dual Outputs
Fabricantes Hitachi Semiconductor 
Logotipo Hitachi Semiconductor Logotipo



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HD74ALVCH16820
3.3-V 10-bit Flip Flops with Dual Outputs
ADE-205-170B (Z)
3rd. Edition
December 1999
Description
The flip flops of the HD74ALVCH16820 are edge triggered D-type flip flops. On the positive transition of
the clock (CLK) input, the device provides true data at the Q outputs. A buffered output enable (OE) input
can be used to place the ten outputs in either a normal logic state (high or low logic level) or a high
impedance state. In the high impedance state, the outputs neither load nor drive the bus lines significantly.
The high impedance state and increased drive provide the capability to drive bus lines without need for
interface or pullup components. OE input does not affect the internal operation of the flip flops. Old data
can be retained or new data can be entered while the outputs are in the high impedance state. Active bus
hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Features
VCC = 2.3 V to 3.6 V
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
High output current ±24 mA (@VCC = 3.0 V)
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors

1 page




HD74ALVCH16820 pdf
Logic Diagram
1OE 1
2OE 28
CLK 56
D1 55
C1
1D
HD74ALVCH16820
2
1Q1
3
1Q2
To nine other channels
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HD74ALVCH16820 arduino
Package Dimensions
14.00
+0.3
–0.1
56
29
1
0.20
+0.1
–0.05
0.50
0.08 M
28
0.40 Max
0.10
HD74ALVCH16820
Unit : mm
8.10 ± 0.3
10° Max
0.50 ± 0.1
Hitachi code
EIAJ code
JEDEC code
TTP-56D
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