PDF BR93H86-WC Data sheet ( Hoja de datos )

Número de pieza	BR93H86-WC
Descripción	EEPROMs Microwire BUS
Fabricantes	ROHM Semiconductor
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No Preview Available ! High Reliability Serial EEPROMs High Reliability Series EEPROMs Microwire BUS BR93L□□-W Series, BR93A□□-WM Series, BR93H□□-WC Series No.11001EGT03 ROHM's series of serial EEPROMs represent the highest level of reliability on the market. A double cell structure provides a failsafe method of data reliability, while a double reset function prevents data miswriting. In addition, gold pads and gold wires are used for internal connections, pushing the boundaries of reliability to the limit. BR93L□□-W Series are assort 1Kbit～16Kbit. BR93A□□-WM Series are possible to operate at 105℃ and are assorted with 1K～16Kbit. BR93H□□-WC Series are possible to operate at 125℃, are assorted with 2K～16Kbit. Contents BR93L□□-W Series BR93L46-W, BR93L56-W, BR93L66-W, BR93L76-W, BR93L86-W BR93A□□-WM Series BR93A46-WM, BR93A56-WM, BR93A66-WM, BR93A76-WM, BR93A86-WM ・・・・P2 BR93H□□-WC Series BR93H56-WC, BR93H66-WC, BR93H76-WC, BR93H86-WC ・・・P22 www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 1/40 2011.09 - Rev.G 1 page BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series Technical Note ●Action timing characteristics (BR93L□□-W, Ta=-40～+85℃, VCC=2.5～5.5V, BR93A□□-WM, Ta=-40～+105℃, VCC=2.5～5.5V) Parameter Symbol 2.5V≦VCC≦5.5V Min. Typ. Max. Unit SK frequency fSK - - 2 MHz SK “H” time SK “L” time tSKH 230 - tSKL 230 - - - ns ns CS “L” time tCS 200 - - ns CS setup time DI setup time tCSS 50 - tDIS 100 - - - ns ns CS hold time tCSH 0- - ns DI hold time Data “1” output delay time tDIH 100 - - tPD1 - - 200 ns ns Data “0” output delay time tPD0 - - 200 ns Time from CS to output establishment Time from CS to High-Z tSV - - 150 ns tDF - - 150 ns Write cycle time tE/W - - 5 ms (BR93L□□-W, Ta=-40～+85℃, VCC=1.8～2.5V) Parameter Symbol SK frequency SK “H” time SK “L” time CS “L” time CS setup time DI setup time CS hold time DI hold time Data “1” output delay time Data “0” output delay time Time from CS to output establishment Time from CS to High-Z Write cycle time fSK tSKH tSKL tCS tCSS tDIS tCSH tDIH tPD1 tPD0 tSV tDF tE/W 1.8V≦VCC≦2.5V Min. Typ. Max. - - 500 0.8 - - 0.8 - - 1- - 200 - - 100 - - 0- - 100 - - - - 0.7 - - 0.7 - - 0.7 - - 200 - -5 Unit kHz us us us ns ns ns ns us us us ns ms ●Sync data input / output timing CS tCSS tSK H tS KL SK t DIS DI DO(READ) tDI H t PD0 tPD1 DO(WRITE) STATUS VALID tCS H tDF Fig.1 Sync data input / output timing ○Data is taken by DI sync with the rise of SK. ○At read action, data is output from DO in sync with the rise of SK. ○The status signal at write (READY / BUSY) is output after tCS from the fall of CS after write command input, at the area DO where CS is “H”, and valid until the next command start bit is input. And, while CS is “L”, DO becomes High-Z. ○After completion of each mode execution, set CS “L” once for internal circuit reset, and execute the following action mode. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 5/40 2011.09 - Rev.G 5 Page BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series Technical Note ●Description of operations Communications of the Microwire Bus are carried out by SK (serial clock), DI (serial data input),DO (serial data output) ,and CS (chip select) for device selection. When to connect one EEPROM to a microcontroller, connect it as shown in Fig.59(a) or Fig.59(b). When to use the input and output common I/O port of the microcontroller, connect DI and DO via a resistor as shown in Fig.59(b) (Refer to pages 17/35.), and connection by 3 lines is available. In the case of plural connections, refer to Fig. 59 (c). Micro- controller CS SK DO BR93LXX /AXX CS SK DI Micro- controller CS SK DO BR93LXX /AXX CS SK DI Micro- controller CS3 CS1 CS0 SK DO DI DI DO DO Device 1 Device 2 Device 3 Fig.59-(a) Connection by 4 lines Fig.59-(b) Connection by 3 lines Fig.59-(c) Connection example of plural devices Fig.59 Connection method with microcontroller Communications of the Microwire Bus are started by the first “1” input after the rise of CS. This input is called a start bit. After input of the start bit, input ope code, address and data. Address and data are input all in MSB first manners. “0” input after the rise of CS to the start bit input is all ignored. Therefore, when there is limitation in the bit width of PIO of the microcontroller, input “0” before the start bit input, to control the bit width. ●Command mode Command Start bit Ope code BR93L46-W BR93A46-WM Address BR93L56/66-W BR93A56/66-WM BR93L76/86-W BR93A76/86-WM Data Read (READ) 1 1 10 A5,A4,A3,A2,A1,A0 A7,A6,A5,A4,A3,A2,A1,A0 A9,A8,A7,A6,A5,A4,A3,A2,A1,A0 D15~D0(READ DATA) Write enable (WEN) 1 00 1 1 * 1 1 ** 1 1 ****** Write (WRITE) 2 1 01 A5,A4,A3,A2,A1,A0 A7,A6,A5,A4,A3,A2,A1,A0 A9,A8,A7,A6,A5,A4,A3,A2,A1,A0 D15~D0(WRITE DATA) Write all (WRAL) 2 1 00 0 1 ** 0 1 ** 0 1 **** D15~D0(WRITE DATA) Write disable (WDS) 1 00 0 0 0 0 ** 0 0 **** Erase (ERASE) 1 11 A5,A4,A3,A2,A1,A0 A7,A6,A5,A4,A3,A2,A1,A0 A9,A8,A7,A6,A5,A4,A3,A2,A1,A0 Chip erase (ERAL) 1 00 1 0 1 0 ** 1 0 ****** ・ Input the address and the data in MSB first manners. ・ As for , input either VIH or VIL. Start bit A7 of BR93L56-W/A56-WM becomes Don't Care. A9 of BR93L76-W/A76-WM becomes Don't Care. Acceptance of all the commands of this IC starts at recognition of the start bit. The start bit means the first “1” input after the rise of CS. 1 As for read, by continuous SK clock input after setting the read command, data output of the set address starts, and address data in significant order are sequentially output continuously. (Auto increment function) 2 When the read and the write all commands are executed, data written in the selected memory cell is automatically deleted, and input data is written. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 11/40 2011.09 - Rev.G 11 Page

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