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부품번호 | NVD4813NH 기능 |
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기능 | Power MOSFET ( Transistor ) | ||
제조업체 | ON Semiconductor | ||
로고 | |||
전체 7 페이지수
NTD4813NH, NVD4813NH
Power MOSFET
30 V, 40 A, Single N−Channel, DPAK/IPAK
Features
• Low RDS(on) to Minimize Conduction Losses
• Low Capacitance to Minimize Driver Losses
• Optimized Gate Charge to Minimize Switching Losses
• Low RG
• AEC−Q101 Qualified and PPAP Capable − NVD4813NH
• These Devices are Pb−Free and are RoHS Compliant
Applications
• CPU Power Delivery
• DC−DC Converters
• High Side Switching
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
C(Nuortreen1t)RqJA
VDSS 30 V
VGS ±20 V
TA = 25°C
ID
9.0 A
TA = 85°C
7.0
Power Dissipation
RqJA (Note 1)
Continuous Drain
C(Nuortreen2t)RqJA
Power Dissipation
RqJA (Note 2)
Continuous Drain
C(Nuortreen1t)RqJC
TA = 25°C
Steady
State
TA = 25°C
TA = 85°C
TA = 25°C
TC = 25°C
TC = 85°C
PD
ID
PD
ID
1.94 W
7.6 A
5.9
1.27 W
40 A
31
Power Dissipation
RqJC (Note 1)
Pulsed Drain
Current
TC = 25°C
tp=10ms TA = 25°C
PD
IDM
35.3 W
90 A
Current Limited by Package
Operating Junction and Storage
Temperature
Source Current (Body Diode)
Drain to Source dV/dt
TA = 25°C
IDmaxPkg
TJ,
TSTG
IS
dV/dt
35
−55 to
+175
29
6
A
°C
A
V/ns
Single Pulse Drain−to−Source Avalanche
Energy (VDD = 24 V, VGS = 10 V,
IL = 17.2 Apk, L = 0.3 mH, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
EAS
44.4 mJ
TL 260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
© Semiconductor Components Industries, LLC, 2011
October, 2011 − Rev. 3
1
http://onsemi.com
V(BR)DSS
30 V
RDS(ON) MAX
13 mW @ 10 V
25.9 mW @ 4.5 V
D
ID MAX
40 A
G
S
N−CHANNEL MOSFET
4
12
3
DPAK
CASE 369AA
(Bent Lead)
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
2
1 Drain 3
Gate Source
Y = Year
WW = Work Week
4813NH = Device Code
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Publication Order Number:
NTD4813NH/D
NTD4813NH, NVD4813NH
TYPICAL PERFORMANCE CURVES
80
10 V
70 8 V
60 6 V
TJ = 25°C
5V
50 4.5 V
40 4.2 V
4V
30 3.8 V
20 3.6 V
3.4 V
10 3.2 V
0 3V
0 2 4 6 8 10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
60
VDS ≥ 10 V
50
40
30
20
TJ = 125°C
10 TJ = 25°C
0 TJ = −55°C
0 246
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
0.04
0.03
ID = 30 A
TJ = 25°C
0.05
0.04
TJ = 25°C
0.02
0.03
0.02
VGS = 4.5 V
0.01
0 2 4 6 8 10 12
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
0.01
VGS = 11.5 V
0
10 15 20 25 30 35 40 45 50 55 60
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.8
ID = 20 A
1.6 VGS = 10 V
10,000
VGS = 0 V
1.4 TJ = 150°C
1.2 1000
1.0
0.8 TJ = 100°C
0.6
−50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
175
100
0
5 10 15 20 25 30
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−to−Source Leakage Current
vs. Drain Voltage
http://onsemi.com
4
4페이지 NTD4813NH, NVD4813NH
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE)
CASE 369AA−01
ISSUE B
L3
L4
b2
e
E
b3
4
12 3
AC
A
B c2
D
DETAIL A
H
bc
0.005 (0.13) M C
L2
GAUGE
PLANE
H
L
L1
DETAIL A
ROTATED 905 CW
A1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
Z
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
C
SEATING
PLANE
INCHES
DIM MIN MAX
A 0.086 0.094
A1 0.000 0.005
b 0.025 0.035
b2 0.030 0.045
b3 0.180 0.215
c 0.018 0.024
c2 0.018 0.024
D 0.235 0.245
E 0.250 0.265
e 0.090 BSC
H 0.370 0.410
L 0.055 0.070
L1 0.108 REF
L2 0.020 BSC
L3 0.035 0.050
L4 −−− 0.040
Z 0.155 −−−
MILLIMETERS
MIN MAX
2.18 2.38
0.00 0.13
0.63 0.89
0.76 1.14
4.57 5.46
0.46 0.61
0.46 0.61
5.97 6.22
6.35 6.73
2.29 BSC
9.40 10.41
1.40 1.78
2.74 REF
0.51 BSC
0.89 1.27
−−− 1.01
3.93 −−−
SOLDERING FOOTPRINT*
6.20
0.244
2.58
0.102
3.00
0.118
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
5.80
0.228
1.60
0.063
6.17
0.243
ǒ ǓSCALE 3:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTD4813NH/D
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