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PDF HD74HCT237 Data sheet ( Hoja de datos )
| Número de pieza | HD74HCT237 | |
| Descripción | 3-to-8-line Decoder/Demultiplexer with Address Latch | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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HD74HCT237
3-to-8-line Decoder/Demultiplexer with Address Latch
Description
The HD74HCT237 decodes a three-bit Address to one-of-eight active-high outputs. The device has a
transparent latch for storage of the Address. Two Chip Selects, one active-low and one active-high, are
provided to facilitate the demultiplexing, cascading, and chip-selecting functions.
The demultiplexing function is accomplished by using the Address inputs to select the desired device
output, and then by using one of the Chip Select as a data input while holding the other one active.
The HD74HCT237 is the noninverting version of the HD74HCT137.
Features
• LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
• High Speed Operation: tpd (A, B, C to Y) = 23 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 4.5 to 5.5 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
1 page  
19.20
20.00 Max
16
9
1
1.3
1.11 Max
8
Unit: mm
7.62
2.54 ± 0.25
0.48 ± 0.10
0.25
+
–
0.13
0.05
0° – 15°
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
DP-16
Conforms
Conforms
1.07 g
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet HD74HCT237.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HD74HCT237 | 3-to-8-line Decoder/Demultiplexer with Address Latch | Hitachi Semiconductor |
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