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부품번호 C8051F972 기능
기능 Low Power Capacitive Sensing MCU
제조업체 Silicon Laboratories
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C8051F972 데이터시트, 핀배열, 회로
C8051F97x
Low Power Capacitive Sensing MCU with up to 32 kB of Flash
Low Power Consumption
- 200 µA/MHz in active mode (24.5 MHz clock)
- 2 µs wakeup time
- 55 nA sleep mode with brownout detector
- 280 nA sleep mode with LFO
- 600 nA sleep mode with external crystal
Capacitance Sense Interface
- Supports buttons, sliders, wheels, and proximity sensing
- Fast 40 µs per channel conversion time
- 16-bit resolution, up to 43 input channels
- Auto scan and wake-on-touch
- Auto-accumulate up to 64x samples
10-Bit Analog-to-Digital Converter
- Up to 43 external pin input channels, up to 300 ksps
- Internal VREF or external VREF supported
Clock Sources
- Internal oscillators: 24.5 MHz, ±2% accuracy supports UART
operation; 20 MHz low power oscillator requires very little bias
current.
- External oscillator: Crystal, RC, C, or CMOS Clock
- SmaRTClock oscillator: 32 kHz Crystal or internal LFO
- Can switch between clock sources on-the-fly; useful in imple-
menting various power-saving modes
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-intrusive in-
system debug (no emulator required)
- Provides breakpoints, single stepping, inspect/modify memory
and registers
Unique Identifier
- 128-bit unique key for each device
High-Speed CIP-51 µC Core
- Efficient, pipelined instruction architecture
- Up to 25 MIPS throughput with 25 MHz clock
- Uses standard 8051 instruction set
- Expanded interrupt handler
- 1-cycle 16 x 16 MAC Engine
- 7-channel Direct Memory Access (DMA) module
Memory
- Up to 32 kB flash
- Flash is in-system programmable in 512-Byte sectors
- Up to 8 kB RAM
General-Purpose I/O
- Up to 43 pins with high sink current and programmable drive
- Crossbar-enabled
Timer/Counters and PWM
- 4 general purpose 16-bit timer/counters
- 16-bit Programmable Counter Array (PCA) with three channels
of PWM, capture/compare, or frequency output capability, and
watchdog timer
Supply Voltage: 1.8 to 3.6 V
- Built-in LDO regulator allows a high analog supply voltage and
low digital core voltage
- 2 supply monitors (brownout detector) for sleep and active
modes
Package Options
- 24-pin QFN (4x4 mm)
- 32-pin QFN (5x5 mm)
- 48-pin QFN (6x6 mm)
Temperature Ranges: –40 to +85 °C
Core / Memory / Support
16-32 kB Flash
4-8 kB RAM
CIP-51
(25 MHz)
Core LDO
Supply Monitor
16-bit CRC
7 ch. DMA 16 x 16 MAC
C2 Serial Debug / Programming
Digital Peripherals
UART
I2C / SMBus HS I2C Slave
SPI
4 x 16-bit Timers
3-Channel PCA / Watchdog
Clocking / Oscillators
24.5 MHz Precision Oscillator
20 MHz Low Power Oscillator
smaRTClock with 16.4 kHz LFO
External Oscillator
Analog Peripherals
SAR ADC (10-bit 300 ksps)
Capacitive Sensing
Voltage Reference
Temperature Sensor
Rev 1.0 5/14
Copyright © 2014 by Silicon Laboratories
C8051F97x




C8051F972 pdf, 반도체, 판매, 대치품
C8051F97x
17.1.ADC0 Analog Multiplexer........................................................................................... 105
17.2.Output Code Formatting ............................................................................................ 106
17.3.Modes of Operation ................................................................................................... 107
17.3.1.Starting a Conversion ........................................................................................107
17.3.2.Tracking Modes ................................................................................................. 108
17.3.3.Burst Mode ........................................................................................................ 109
17.3.4.Settling Time Requirements .............................................................................. 110
17.3.5.Gain Setting....................................................................................................... 110
17.4.8-Bit Mode.................................................................................................................. 110
17.5.Low Power Mode ....................................................................................................... 111
17.6.Window Detector In Single-Ended Mode ...................................................................111
17.7.Voltage Reference ..................................................................................................... 112
17.7.1.External Voltage Reference............................................................................... 112
17.7.2.Internal Voltage Reference................................................................................ 113
17.8.Temperature Sensor .................................................................................................. 113
17.8.1.Calibration ......................................................................................................... 113
17.9.ADC Control Registers...............................................................................................114
17.10.Voltage Reference Registers ................................................................................... 127
17.11.Temperature Sensor Registers................................................................................ 128
18. Capacitive Sense (CS0) ................................................................................................... 130
18.1.Configuring Port Pins as Capacitive Sense Inputs .................................................... 131
18.2.Initializing the Capacitive Sensing Peripheral ............................................................131
18.3.Capacitive Sense Start-Of-Conversion Sources........................................................ 131
18.4.CS0 Multiple Channel Enable .................................................................................... 132
18.5.CS0 Gain Adjustment ................................................................................................ 132
18.6.Wake from Suspend .................................................................................................. 132
18.7.Using CS0 in Applications that Utilize Sleep Mode.................................................... 132
18.8.Automatic Scanning (Method 1—CS0SMEN = 0) .....................................................132
18.9.Automatic Scanning (Method 2—CS0SMEN = 1) .....................................................134
18.10.CS0 Comparator ......................................................................................................134
18.11.CS0 Conversion Accumulator.................................................................................. 135
18.12.CS0 Pin Monitor....................................................................................................... 136
18.13.Adjusting CS0 For Special Situations ...................................................................... 137
18.13.1.Adjusting the CS0 Reset Timing...................................................................... 137
18.13.2.Adjusting Primary Reset Timing: CS0DT ........................................................ 137
18.13.3.Adjusting Secondary Reset Timing: CS0DR ................................................... 138
18.13.4.Adjusting CS0 Ramp Timing: CS0IA ............................................................... 138
18.13.5.Low-Pass Filter Adjustments ........................................................................... 139
18.13.6.Adjusting CS0 Ramp Timing: CS0RP ............................................................. 139
18.13.7.Adjusting CS0LP for Non-Default CS0RP Settings ......................................... 139
18.13.8.Other Options for Adjusting CS0LP................................................................. 139
18.14.CS0 Analog Multiplexer ........................................................................................... 140
18.14.1.Pin Configuration for CS0 Measurements Method .......................................... 142
18.15.Capacitive Sense Registers..................................................................................... 143
19. Analog Multiplexer (AMUX0)........................................................................................... 158
19.1.AMUX Control Registers............................................................................................ 159
4 Rev 1.0

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C8051F972 전자부품, 판매, 대치품
C8051F97x
27.7.Flash Error Reset....................................................................................................... 326
27.8.Software Reset .......................................................................................................... 326
27.9.Reset Sources Control Registers............................................................................... 327
27.10.Supply Monitor Control Registers ............................................................................ 328
28. Serial Peripheral Interface (SPI0) ................................................................................... 329
28.1.Signal Descriptions .................................................................................................... 330
28.1.1.Master Out, Slave In (MOSI) ............................................................................. 330
28.1.2.Master In, Slave Out (MISO) ............................................................................. 330
28.1.3.Serial Clock (SCK)............................................................................................. 330
28.1.4.Slave Select (NSS)............................................................................................ 330
28.2.SPI0 Master Mode Operation .................................................................................... 331
28.3.SPI0 Slave Mode Operation ...................................................................................... 333
28.4.SPI0 Interrupt Sources...............................................................................................333
28.5.Serial Clock Phase and Polarity.................................................................................333
28.6.SPI Special Function Registers .................................................................................335
28.7.SPI Control Registers ................................................................................................ 339
29. System Management Bus / I2C (SMBus0) ..................................................................... 343
29.1.Supporting Documents .............................................................................................. 344
29.2.SMBus Configuration ................................................................................................. 344
29.3.SMBus Operation....................................................................................................... 344
29.3.1.Transmitter vs. Receiver.................................................................................... 345
29.3.2.Arbitration .......................................................................................................... 345
29.3.3.Clock Low Extension ......................................................................................... 345
29.3.4.SCL Low Timeout .............................................................................................. 345
29.3.5.SCL High (SMBus Free) Timeout...................................................................... 346
29.4.Using the SMBus ....................................................................................................... 346
29.4.1.SMBus Configuration Register ..........................................................................346
29.4.2.SMBus Pin Swap...............................................................................................348
29.4.3.SMBus Timing Control....................................................................................... 348
29.4.4.SMB0CN Control Register.................................................................................348
29.4.5.Hardware Slave Address Recognition............................................................... 350
29.4.6.Data Register..................................................................................................... 350
29.5.SMBus Transfer Modes ............................................................................................. 351
29.5.1.Write Sequence (Master)................................................................................... 351
29.5.2.Read Sequence (Master) .................................................................................. 352
29.5.3.Write Sequence (Slave)..................................................................................... 353
29.5.4.Read Sequence (Slave) .................................................................................... 354
29.6.SMBus Status Decoding ............................................................................................ 354
29.7.I2C / SMBus Control Registers .................................................................................. 359
30. I2C Slave ...........................................................................................................................365
30.1.Supporting Documents .............................................................................................. 366
30.2.The I2C Configuration................................................................................................ 366
30.3.I2CSLAVE0 Operation ...............................................................................................366
30.3.1.Transmitter vs. Receiver.................................................................................... 367
30.3.2.Clock Stretching ................................................................................................ 367
30.3.3.SCL Low Timeout .............................................................................................. 368
Rev 1.0
7

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