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PDF MAX5522 Data sheet ( Hoja de datos )
| Número de pieza | MAX5522 | |
| Descripción | Voltage-Output DACs | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-3064; Rev 1; 12/04
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
General Description
The MAX5522–MAX5525 are dual, 10-bit, ultra-low-
power, voltage-output, digital-to-analog converters
(DACs) offering rail-to-rail buffered voltage outputs. The
DACs operate from a 1.8V to 5.5V supply and consume
less than 5µA, making the devices suitable for low-
power and low-voltage applications. A shutdown mode
reduces overall current, including the reference input
current, to just 0.18µA. The MAX5522–MAX5525 use a
3-wire serial interface that is compatible with SPI™,
QSPI™, and MICROWIRE™.
Upon power-up, the MAX5522–MAX5525 outputs are
driven to zero scale, providing additional safety for
applications that drive valves or for other transducers
that need to be off during power-up. The zero-scale
outputs enable glitch-free power-up.
The MAX5522 accepts an external reference input and
provides unity-gain outputs. The MAX5523 contains a
precision internal reference and provides a buffered
external reference output with unity-gain DAC outputs.
The MAX5524 accepts an external reference input and
provides force-sense outputs. The MAX5525 contains a
precision internal reference and provides a buffered
external reference output with force-sense DAC outputs.
The MAX5524/MAX5525 are available in a 4mm x 4mm
x 0.8mm, 12-pin, thin QFN package. The MAX5522/
MAX5523 are available in an 8-pin µMAX package. All
devices are guaranteed over the extended -40°C to
+85°C temperature range.
For 12-bit compatible devices, refer to the MAX5532–
MAX5535 data sheet. For 8-bit compatible devices,
refer to the MAX5512–MAX5515 data sheet.
Applications
Portable Battery-Powered Devices
Instrumentation
Automatic Trimming and Calibration in Factory
or Field
Programmable Voltage and Current Sources
Industrial Process Control and Remote
Industrial Devices
Remote Data Conversion and Monitoring
Chemical Sensor Cell Bias for Gas Monitors
Programmable LCD Bias
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Features
♦ Ultra-Low 5µA Supply Current
♦ Shutdown Mode Reduces Supply Current to
0.18µA (max)
♦ Single +1.8V to +5.5V Supply
♦ Small 4mm x 4mm x 0.8mm Thin QFN Package
♦ Internal Reference Sources 8mA of Current
(MAX5523/MAX5525)
♦ Flexible Force-Sense-Configured Rail-to-Rail
Output Buffers
♦ Fast 16MHz, 3-Wire, SPI-/QSPI-/MICROWIRE-
Compatible Serial Interface
♦ TTL- and CMOS-Compatible Digital Inputs with
Hysteresis
♦ Glitch-Free Outputs During Power-Up
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
MAX5522EUA
-40°C to +85°C 8 µMAX
MAX5523EUA
-40°C to +85°C 8 µMAX
MAX5524ETC
-40°C to +85°C 12 Thin QFN-EP*
MAX5525ETC
-40°C to +85°C 12 Thin QFN-EP*
*EP = Exposed paddle (internally connected to GND).
Selector Guide
PART
MAX5522EUA
MAX5523EUA
MAX5524ETC
MAX5525ETC
OUTPUTS
Unity gain
Unity gain
Force sense
Force sense
REFERENCE
External
Internal
External
Internal
TOP MARK
—
—
AACK
AACL
Pin Configurations
TOP VIEW
CS 1
SCLK 2
DIN 3
REFIN(MAX5522) 4
REFOUT(MAX5523)
MAX5522
MAX5523
8 OUTA
7 GND
6 VDD
5 OUTB
µMAX
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
TIMING CHARACTERISTICS
(VDD = +4.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
TIMING CHARACTERISTICS (VDD = 4.5V to 5.5V )
Serial Clock Frequency
DIN to SCLK Rise Setup Time
fSCLK
tDS
DIN to SCLK Rise Hold Time
tDH
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Pulse-Width High
SCLK Rise to CS Rise Hold Time
CS Fall to SCLK Rise Setup Time
SCLK Fall to CS Fall Setup
CS Rise to SCK Rise Hold Time
tCH
tCL
tCSW
tCSH
tCSS
tCSO
tCS1
CONDITIONS
MIN TYP
0
15
0
24
24
100
0
20
0
20
MAX
16.7
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING CHARACTERISTICS
(VDD = +1.8V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
TIMING CHARACTERISTICS (VDD = 1.8V to 5.5V )
Serial Clock Frequency
fSCLK
DIN to SCLK Rise Setup Time
tDS
DIN to SCLK Rise Hold Time
tDH
SCLK Pulse-Width High
tCH
SCLK Pulse-Width Low
CS Pulse-Width High
tCL
tCSW
SCLK Rise to CS Rise Hold Time
tCSH
CS Fall to SCLK Rise Setup Time
tCSS
SCLK Fall to CS Fall Setup
CS Rise to SCK Rise Hold Time
tCSO
tCS1
0 10 MHz
24 ns
0 ns
40 ns
40 ns
150 ns
0 ns
30 ns
0 ns
30 ns
Note 1: Linearity is tested within codes 24 to 1020.
Note 2: Offset is tested at code 24.
Note 3: Gain is tested at code 1023. For the MAX5524/MAX5525, FB_ is connected to its respective OUT_.
Note 4: Guaranteed by design. Not production testsed
Note 5: VDD must be a minimum of 1.8V.
Note 6: Outputs can be shorted to VDD or GND indefinitely, provided that package power dissipation is not exceeded.
Note 7: Optimal noise performance is at 2nF load capacitance.
Note 8: Thermal hysteresis is defined as the change in the initial +25°C output voltage after cycling the device from TMAX to TMIN.
Note 9: All digital inputs at VDD or GND.
Note 10: Load = 10kΩ in parallel with 100pF, VDD = 5V, VREF = 4.096V (MAX5522/MAX5524) or VREF = 3.9V (MAX5523/MAX5525).
_______________________________________________________________________________________ 5
5 Page 
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
Pin Description
MAX5522
1
2
3
4
—
—
—
5
6
7
8
—
—
PIN
MAX5523 MAX5524
11
22
33
—4
4—
— 5, 11
—6
57
68
79
8 10
— 12
— EP
MAX5525
1
2
3
—
4
5, 11
6
7
8
9
10
12
EP
NAME
FUNCTION
CS
SCLK
Active-Low Digital Chip-Select Input
Serial-Interface Clock Input
DIN
REFIN
REFOUT
Serial-Interface Data Input
Reference Input
Reference Output
N.C.
No Connection. Leave N.C. inputs unconnected
(floating) or connected to GND.
FBB
OUTB
Channel B Feedback Input
Channel B Analog Voltage Output
VDD
GND
OUTA
Power Input. Connect VDD to a 1.8V to 5.5V power
supply. Bypass VDD to GND with a 0.1µF capacitor.
Ground
Channel A Analog Voltage Output
FBA Channel A Feedback Input
Exposed Paddle Exposed Paddle. Connect EP to GND.
Functional Diagrams
SCLK
DIN
CS
POWER-
DOWN
CONTROL
CONTROL
LOGIC
AND
SHIFT
REGISTER
VDD REFIN
MAX5522
INPUT
REGISTER
DAC
REGISTER
10-BIT DAC
INPUT
REGISTER
DAC
REGISTER
10-BIT DAC
OUTA
OUTB
GND
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet MAX5522.PDF ] | |
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