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9LPRS525 PDF 데이터시트 ( Data , Function )

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기능 ICS9LPRS525
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9LPRS525 데이터시트, 핀배열, 회로
DATASHEET
56-pin CK505 for Intel Systems
ICS9LPRS525
Recommended Application:
56-pin CK505 compatible clock, w/fully integrated Vreg and series
resistors on differential outputs
Output Features:
• 2 - CPU differential low power push-pull pairs
• 7 - SRC differential push-pull pairs
• 1 - CPU/SRC selectable differential low power push-pull pair
• 1 - SRC/DOT selectable differential low power push-pull pair
• 1 - SRC/SE selectable differential push-pull pair/Single-ended
outputs
• 5 - PCI, 33MHz
• 1 - USB, 48MHz
• 1 - REF, 14.318MHz
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• SRC output cycle-cycle jitter < 125ps
• PCI outputs cycle-cycle jitter < 250ps
• +/- 100ppm frequency accuracy on all outputs
• SRC outputs meet PCIe Gen2 when sourced from PLL3
Features/Benefits:
• Supports spread spectrum modulation, 0 to -0.5% down
spread
• Supports CPU clks up to 400MHz
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
Table 1: CPU Frequency Select Table
FSLC2
B0b7
0
0
0
0
1
1
1
1
FSLB1
B0b6
0
0
1
1
0
0
1
1
FSLA1
B0b5
0
1
0
1
0
1
0
1
CPU
MHz
266.66
133.33
200.00
166.66
333.33
100.00
400.00
SRC PCI REF USB DOT
MHz MHz MHz MHz MHz
100.00 33.33 14.318 48.00 96.00
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Pin Configuration
PCI0/CR#_A 1
56 SCLK
VDDPCI 2
PCI1/CR#_B 3
PCI2/TME 4
PCI3/CFG0 5
PCI4/SRC5_EN 6
PCI_F5/ITP_EN 7
GNDPCI 8
VDD48 9
USB_48MHz/FSLA 10
GND48 11
VDD96IO 12
DOTT_96_LRS/SRCT0_LRS 13
DOTC_96_LRS/SRCC0_LRS 14
GND 15
VDD 16
SRCT1_LRS/SE1 17
SRCC1_LRS/SE2 18
GND 19
VDDPLL3IO 20
SRCT2_LRS/SATAT_LRS 21
SRCC2_LRS/SATAC_LRS 22
GNDSRC 23
SRCT3_LRS/CR#_C 24
SRCC3_LRS/CR#_D 25
VDDSRCIO 26
SRCT4_LRS 27
SRCC4_LRS 28
55 SDATA
54 REF0/FSLC/TEST_SEL
53 VDDREF
52 X1
51 X2
50 GNDREF
49 FSLB/TEST_MODE
48 CK_PWRGD/PD#
47 VDDCPU
46 CPUT0_LRS
45 CPUC0_LRS
44 GNDCPU
43 CPUT1_F_LRS
42 CPUC1_F_LRS
41 VDDCPUIO
40 NC
39 CPUT2_ITP_LRS/SRCT8_LRS
38 CPUC2_ITP_LRS/SRCC8_LRS
37 VDDSRCIO
36 SRCT7_LRS/CR#_F
35 SRCC7_LRS/CR#_E
34 GNDSRC
33 SRCT6_LRS
32 SRCC6_LRS
31 VDDSRC
30 PCI_STOP#/SRCT5_LRS
29 CPU_STOP#/SRCC5_LRS
56-SSOP & TSSOP
IDTTM PC MAIN CLOCK
1
1484C—04/20/10




9LPRS525 pdf, 반도체, 판매, 대치품
ICS9LPRS525
PC MAIN CLOCK
General Description
ICS9LPRS525 is compliant Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for Intel desktop
chipsets. ICS9LPRS525 is driven with a 14.318MHz crystal. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express
support.
Block Diagram
X1
X2 OSC
REF
REF
CPU(1:0)
CPU PLL1
SS
CPU
SRC
SRC_MAIN
SRC8/ITP
SRC(7:3)
PLL3
SS
SRC
PCI33MHz
FSLA
CKPWRGD/PD#
PCI_STOP#
CPU_STOP#
CR#_(A:F)
SRC5_EN
ITP_EN
FSLC/TESTSEL
FSLB/TESTMODE
Control
Logic
PLL2
Non-SS
SATA
DOT96MHz
48MHz
PCI33MHz
Differential Output
SE Outputs
7
PCI(5:0)
SRC2/SATA
SRC1/SE(2:1)
SRC0/DOT96
48MHz
Power Groups
Pin Number
VDD
GND
41, 47
44
16 15
26, 31, 37
23, 34
20
12
9
53
2
IDTTM PC MAIN CLOCK
19
11
11
50
8
Description
CPUCLK
Master Clock, Analog
SRCCLK
PLL3/SE
DOT 96Mhz
USB 48
Xtal, REF
PCICLK
4
1484C—04/20/10

4페이지










9LPRS525 전자부품, 판매, 대치품
ICS9LPRS525
PC MAIN CLOCK
PPM tolerance
Cycle to Cycle Jitter
Spread
Differential Clock Tolerances
CPU
SRC
DOT96
BMC133
100 100
100
100
85 125 250
125
-0.50%
-0.50%
0
-0.50%
ppm
ps
%
Clock Periods - Differential Outputs with Spread Spectrum Disabled
Measurement Window
SSC OFF
Center
Freq.
MHz
1 Clock
1us
0.1s
-SSC
- ppm
-c2c jitter Short-Term Long-Term
AbsPer Average Average
Min Min
Min
0.1s
0 ppm
Period
Nominal
0.1s
+ ppm
Long-Term
Average
Max
100.00 9.91400
9.99900 10.00000 10.00100
133.33 7.41425
7.49925
7.50000
7.50075
CPU
166.67
200.00
5.91440
4.91450
5.99940
4.99950
6.00000
5.00000
6.00060
5.00050
266.67 3.66462
3.74962
3.75000
3.75037
333.33 2.91470
2.99970
3.00000
3.00030
400.00 2.41475
2.49975
2.50000
2.50025
SRC/SATA 100.00 9.87400
9.99900 10.00000 10.00100
DOT96
96.00 10.16563
10.41563 10.41667 10.41771
1us
+SSC
Short-Term
Average
Max
1 Clock
+c2c jitter Units Notes
AbsPer
Max
10.08600 ns 1,2
7.58575 ns 1,2
6.08560 ns 1,2
5.08550 ns 1,2
3.83537 ns 1,2
3.08530 ns 1,2
2.58525 ns 1,2
10.12600 ns 1,2
10.66771 ns 1,2
Clock Periods - Differential Outputs with Spread Spectrum Enabled
Measurement Window
SSC ON
Center
Freq.
MHz
1 Clock
1us
0.1s
-c2c jitter
AbsPer
-SSC
Short-Term
Average
- ppm
Long-Term
Average
Min Min
Min
0.1s
0 ppm
Period
Nominal
0.1s
+ ppm
Long-Term
Average
Max
99.75 9.91406 9.99906 10.02406 10.02506 10.02607
133.00 7.41430 7.49930 7.51805
7.51880
7.51955
CPU
166.25
199.50
5.91444
4.91453
5.99944
4.99953
6.01444
5.01203
6.01504
5.01253
6.01564
5.01303
266.00 3.66465 3.74965 3.75902
3.75940
3.75977
332.50 2.91472 2.99972 3.00722
3.00752
3.00782
399.00 2.41477 2.49977 2.50602
2.50627
2.50652
SRC
99.75 9.87406 9.99906 10.02406 10.02506 10.02607
1us
+SSC
Short-Term
Average
Max
10.05107
7.53830
6.03064
5.02553
3.76915
3.01532
2.51277
10.05107
1 Clock
+c2c jitter Units Notes
AbsPer
Max
10.13607 ns 1,2
7.62330 ns 1,2
6.11564 ns 1,2
5.11053 ns 1,2
3.85415 ns 1,2
3.10032 ns 1,2
2.59777 ns 1,2
10.17607 ns 1,2
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy specifications are guaranteed with the assumption that the crystal input is tuned to exactly 14.31818MHz.
IDTTM PC MAIN CLOCK
7
1484C—04/20/10

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