PDF AN11130 Data sheet ( Hoja de datos )

Número de pieza	AN11130
Descripción	Bias module
Fabricantes	NXP Semiconductors
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No Preview Available ! AN11130 Bias module for 50 V GaN demonstration boards Rev. 1 — 8 December 2011 Application note Document information Info Content Keywords GaN, bias Abstract This application note describes a bias controller module for GaN HEMT RF power transistors. It provides constant quiescent drain current with temperature, special bias and power sequencing, and overcurrent protection. 1 page NXP Semiconductors AN11130 Bias module for 50 V GaN demonstration boards 6. Circuit description 6.1 Negative voltage generation The bias controller uses a switched-capacitor voltage inverter, U1, to generate a regulated 4 V from a single positive supply. The +5 V supply is generated from the high-voltage drain supply by linear regulator U4. U1 operates at a switching frequency of approximately 550 kHz; C3, R4, and C10 are used to reduce output ripple to less than 2 mV (p-p). When the output voltage is within 5 % of the 4 V set value, the REG output goes LOW. The REG output LOW signal acts as an active-LOW (power valid) signal to enable drain power to the GaN device. +VD_IN U4 IN 8 1 OUT C9 2.2 μF LT3010EMS8E−5 EN 5 2 SENSE GND:4,9 U1 +5V C7 1 μF VCC 1 6 OUT R9 SHDN 8 10 kΩ LTC1261CS8−4 R4 C3 10 Ω 10 μF −4V C10 10 μF C1+ 2 7 REG POWER_VALID_N C4 100 nF C1− 3 5 COMP GND:4 C6 100 pF aaa-001667 Fig 2. +5 V and 4 V voltage generation circuit 6.2 Drain voltage switching Most lower power HEMT bias controllers use a P-channel power MOSFET as the drain voltage load switch. This has the advantage of simplicity, often requiring nothing more than level-shifting transistors between the voltage inverter ‘power valid’ signal and the MOSFET gate. However, as load currents increase above 2 A to 5 A, the required MOSFET becomes large and expensive. Consequently, this bias controller uses a common hot-swap controller IC, U2 to drive an inexpensive N-channel MOSFET. AN11130 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2011 © NXP B.V. 2011. All rights reserved. 5 of 14 5 Page xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx L1 BLM21BD102 U4 LT3010EMS8E−5 IN 8 C9 1 μF C12 1 μF EN 5 GND:4,9 1 OUT 2 SENSE +5V C7 1 μF U1 LTC1261CS8−4 VCC 1 R9 SHDN 8 10 kΩ C1+ 2 C4 100 nF C1− 3 GND:4 6 OUT 7 REG 5 COMP C6 100 pF R4 10 Ω C3 10 μF 3 1 Q1 BSH103 2 D1 HSMG−C170 green = VG on R1 1 kΩ 2 BSS84 Q3 3 1 R2 100 kΩ R16 10 kΩ 3 1 2 Q2 BSH103 D3 31 BAW56 D3 32 BAW56 U3 LM7321MF 35 1 42 S1 1437575−1 standby 32 1 VD on R17 68.1 kΩ R3 10 kΩ C5 100 nF R12 10 kΩ R8 1 kΩ 1 Q4 BSH103 32 D2 HSMY−C170 yellow = VD on R11 100 kΩ C8 1 μF R20 -4V R13 2 kΩ 1 R5 2 1 kΩ 3 R10 10 kΩ R14 2 kΩ R6 30.1 kΩ C2 100 nF R19 3.01 kΩ 1 kΩ C10 10 μF R7 44.2 kΩ R18 10 kΩ 7 C temperature 8 B compensation 9 E npn transistor R24 10 Ω U2 LT4256-1CS8 VCC 8 7 SENSE UV 1 6 GATE 2 FB TIMER 5 C11 100N GND:4 3 PGD 10 VG 11 FB 12 D4 BZX384-C11 6 5 V+ 4 D drain 3 G switching 2 S npn mosfet 1 R22 10 Ω R21 75 kΩ R23 100 Ω C1 10 nF R15 10 kΩ aaa-001673 Fig 8. Bias module schematic 11 Page

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