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PDF FXLP4555MPX Data sheet ( Hoja de datos )
| Número de pieza | FXLP4555MPX | |
| Descripción | 1.8V / 3.0V SIM Card Power Supply and Level Shifter | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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May 2011
FXLP4555
1.8V / 3.0V SIM Card Power Supply and Level Shifter
Features
Supports 1.8V or 3.0V SIM Cards
LDO Supplies >50mA Under 1.8V and 3.0V
Built-in Pull-up Resistor for I/O Pin in Both
Directions
ESD Protection: 8kV (Human Body Model,
According to ISO-7816 Specifications)
Supports Clock 5MHz
Supports “Clock Stop” Power Management per
ISO7816-3 Specifications
Low-Profile 3x3mm MLP-16 Package
Applications
SIM Card Interface Circuit for 2G, 2.5G, and 3G
Mobile Phones
Identification Module
Smart Card Readers
Wireless PC Cards
Description
The FXLP4555 is a level-shifter analog circuit designed
to translate the voltages between a SIM card and an
external baseband. A built-in LDO-type DC-DC
converter allows the FXLP4555 to drive 1.8V and 3.0V
SIM cards. The device fulfills the ISO7816-3 smart-card
interface standard as well as GSM 11.11 (11.12 and
11.18) and 3G mobile requirements (IMT-2000/3G UICC
standard). The EN pin enables a low-current Shutdown
Mode that extends battery life. The card power supply
voltage (VCC_C) is selected using a single pin (VSEL).
Ordering Information
Part Number
Operating
Temperature Range
FXLP4555MPX
-40 to +85°C
Top
Mark
FXLP
4555
Package
16-Lead,MLP,Quad,JEDEC
MO-220,3MM Square
Packing Method
3000 Units
on Tape & Reel
© 2010 Fairchild Semiconductor Corporation
FXLP4555 • Rev. 1.0.0
www.fairchildsemi.com
1 page  
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. TA=+25°C.
Symbol
VBAT
VCCA
VCC_C
VIN
IIN
VOUT
IOUT
VOUT_SIM
IOUT_SIM
PD
ΘJA
TA
TJ
TJMAX
TSTG
ESD
Parameter
LDO Power Supply Voltage
Power Supply from Baseband Side
External Card Power Supply
Digital Input Pin Voltage
Digital Input Pin Current
Digital Output Pin Voltage
Digital Output Pin Current
SIM Card Output Pin Voltage
SIM Card Output Pin Current(1)
Power Dissipation at TA=+85°C
Thermal Resistance, Junction-to-Air
Operating Ambient Temperature Range
Operating Junction Temperature Range
Maximum Junction Temperature
Storage Temperature Range
Electrostatic
Discharge
Capability
Human Body
Model,
JESD22-A114
R=1500Ω,
C=100pF
SIM Card Pins
(7,8,9,10,11)
All Other Pins
Min.
-0.5
-0.5
-0.5
-0.5
-5
-0.5
-10
-0.5
-40
-40
-65
Typ.
VBAT
VCCA
VCC_C
VIN
VOUT
VOUT
8000
Max.
6.0
6.0
6.0
VCCA+0.5,
but <6.0
+5
VCCA+0.5,
but <6.0
+10
SIM_VCC+
0.5<6.0
15
440
72
+85
+125
+125
+150
Unit
V
V
V
V
mA
V
mA
V
mA
mW
°C/W
°C
°C
°C
°C
2000
V
Charged
SIM Card Pins
Device Model, (7,8,9,10,11)
JESD22-C101 All Other Pins
Moisture Sensitivity Level
Notes:
1. Internally limited.
2. Meets or exceeds JEDEC specification EIA/JESD78 IC latchup test.
2000
600
1
Level
© 2010 Fairchild Semiconductor Corporation
FXLP4555 • Rev. 1.0.0
5
www.fairchildsemi.com
5 Page 
Applications Information (Continued)
Input Schmitt Triggers
All the logic input pins (except I/O_H and I/O_C) have
built-in Schmitt trigger circuits to prevent uncontrolled
operation. Typical dynamic characteristics of the related
pins are depicted in Figure 11.
The output signal is guaranteed to go HIGH when the
input voltage is above 0.7 x VDD and go LOW when the
input voltage is below 0.4V. See Electrical
Characteristics section.
Shutdown Operating
To save power, it is possible to put the FXLP4555 in
Shutdown Mode by setting the pin EN LOW. The device
enters Shutdown Mode automatically when VCCA goes
lower than 1.1V typically.
ESD Protection
The FXLP4555 SIM interface features an HBM ESD
voltage protection in excess of 7kV for all the SIM pins
(IO_C, CLK_C, RST_C, VCC_C and GND). All the other
pins (Host side) sustain at least 2kV. The HBM ESD
voltage required by the ISO7816 standard is 4kV.
Printed Circuit Board (PCB) Layout
Careful layout routing should be applied to achieve
efficient operating of the device in its mobile or portable
environment and to fully exploit its performance.
The bypass capacitors must be connected as close as
possible to the device pins (VCC_C, VCCA, or VBAT) to
reduce possible parasitic behaviors (ripple and noise). It
is recommended to use ceramic capacitors.
The exposed pad should be connected to ground as
well as the unconnected pins (NC). A relatively large
ground plane is recommended.
Clock Stop
Section 6.3.2 of ISO7816-3 identifies the “Power
Management” feature of Clock Stop. For cards
supporting Clock Stop, when the interface device
expects no transmission from the card and when I/O
has remained at state H for at least 1,860 clock cycles
(delay tg), then according to Figure 13, the interface
device may stop the clock on CLK (at time te) while the
SIM card VCC remains powered and RST at state H.
Figure 12.
When the clock is stopped (from time te to time tf), CLK
shall be maintained either at state H or at state L,
according to the clock stop indicator X defined in section
8.3 of the ISO7816-3 specification.
At time tf, the interface device restarts the clock and the
information exchange on I/O may continue after at least
700 clock cycles (at time tf + th).
Clock Stop
The FXLP4555 supports the above description of Clock
Stop per ISO7816-3 specifications.
© 2010 Fairchild Semiconductor Corporation
FXLP4555 • Rev. 1.0.0
11
www.fairchildsemi.com
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet FXLP4555MPX.PDF ] | |
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