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PDF 56F807 Data sheet ( Hoja de datos )

Número de pieza 56F807
Descripción 16-bit Digital Signal Controllers
Fabricantes Freescale Semiconductor 
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No Preview Available ! 56F807 Hoja de datos, Descripción, Manual

56F807
Data Sheet
Preliminary Technical Data
56F800
16-bit Digital Signal Controllers
DSP56F807
Rev. 16
09/2007
freescale.com

1 page




56F807 pdf
56F807 Description
• Two dedicated General Purpose Quad Timers totaling six pins: Timer C with two pins and Timer D with
four pins
• CAN 2.0 B Module with 2-pin port for transmit and receive
• Two Serial Communication Interfaces each with two pins (or four additional GPIO lines)
• Serial Peripheral Interface (SPI) with configurable 4-pin port (or four additional GPIO lines)
• Computer-Operating Properly (COP) Watchdog timer
• Two dedicated external interrupt pins
• 14 dedicated General Purpose I/O (GPIO) pins, 18 multiplexed GPIO pins
• External reset input pin for hardware reset
• External reset output pin for system reset
• JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
• Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock
1.1.4 Energy Information
• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
• Uses a single 3.3V power supply
• On-chip regulators for digital and analog circuitry to lower cost and reduce noise
• Wait and Stop modes available
1.2 56F807 Description
The 56F807 is a member of the 56800 core-based family of processors. It combines, on a single chip, the
processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to
create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact
program code, the 56F807 is well-suited for many applications. The 56F807 includes many peripherals
that are especially useful for applications such as motion control, smart appliances, steppers, encoders,
tachometers, limit switches, power supply and control, automotive control, engine management, noise
suppression, remote utility metering, industrial control for power, lighting, and automation.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and
optimized instruction set allow straightforward generation of efficient, compact DSP and control code.
The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized
control applications.
The 56F807 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F807 also provides two external
dedicated interrupt lines and up to 32 General Purpose Input/Output (GPIO) lines, depending on peripheral
configuration.
The 56F807 controller includes 60K, 16-bit words of Program Flash and 8K words of Data Flash (each
programmable through the JTAG port) with 2K words of Program RAM and 4K words of Data RAM. It
also supports program execution from external memory.
Freescale Semiconductor
56F807 Technical Data Technical Data, Rev. 16
5

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56F807 arduino
2.3 Clock and Phase Locked Loop Signals
Clock and Phase Locked Loop Signals
No. of
Pins
1
1
1
Signal
Name
EXTAL
XTAL
CLKO
Table 2-5 PLL and Clock
Signal
Type
Input
Input/
Output
State During
Reset
Input
Chip-driven
Signal Description
External Crystal Oscillator Input—This input should be connected to
an 8MHz external crystal or ceramic resonator. For more information,
please refer to Section 3.4.
Crystal Oscillator Output—This output should be connected to an
8MHz external crystal or ceramic resonator. For more information, please
refer to Section 3.4.
Output
Chip-driven
This pin can also be connected to an external clock source. For more
information, please refer to Section 3.4.2.
Clock Output—This pin outputs a buffered clock signal. By programming
the CLKOSEL[4:0] bits in the CLKO Select Register (CLKOSR), the user
can select between outputting a version of the signal applied to XTAL and
a version of the device’s master clock at the output of the PLL. The clock
frequency on this pin can also be disabled by programming the
CLKOSEL[4:0] bits in CLKOSR.
2.4 Address, Data, and Bus Control Signals
Table 2-6 Address Bus Signals
No. of
Pins
6
2
Signal
Name
A0–A5
A6–A7
Signal
Type
Output
Output
State During
Reset
Tri-stated
Tri-stated
Signal Description
Address Bus—A0–A5 specify the address for external Program or
Data memory accesses.
Address Bus—A6–A7 specify the address for external Program or
Data memory accesses.
GPIOE2- Input/O
GPIOE3 utput
Input
Port E GPIO—These two General Purpose I/O (GPIO) pins can
individually be programmed as input or output pins.
After reset, the default state is Address Bus.
8
A8–A15 Output
Tri-stated Address Bus—A8–A15 specify the address for external Program or
Data memory accesses.
GPIOA0- Input/O
GPIOA7 utput
Input
Port A GPIO—These eight General Purpose I/O (GPIO) pins can be
individually programmed as input or output pins.
After reset, the default state is Address Bus.
Freescale Semiconductor
56F807 Technical Data Technical Data, Rev. 16
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