Datasheet.kr   

AR9344 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 AR9344
기능 Highly-Integrated and Feature-Rich IEEE 802.11n 2x2 2.4/5 GHz Premium SoC
제조업체 Atheros
로고 Atheros 로고 



전체 70 페이지

		

No Preview Available !

AR9344 데이터시트, 핀배열, 회로
Data Sheet
PRELIMINARY
December 2010
AR9344 Highly-Integrated and Feature-Rich IEEE 802.11n 2x2
2.4/5 GHz Premium SoC for Advanced WLAN Platforms
General Description
The Atheros AR9344 is a highly integrated and
feature-rich IEEE 802.11n 2x2 2.4/5 GHz System-
on-a-Chip (SoC) for advanced WLAN platforms.
It includes a MIPS 74Kc processor, PCI Express
1.1 Root Complex and Endpoint interfaces, five
port IEEE 802.3 Fast Ethernet Switch with MAC/
PHY, one MII/RMII/RGMII interface, one USB
2.0 MAC/PHY, and external memory interface
for serial Flash, SDRAM, DDR1 or DDR2, I2S/
SPDIF-Out audio interface, SLIC VOIP/PCM
interface, two UARTs, and GPIOs that can be
used for LED controls or other general purpose
interface configurations.
The AR9344 supports 802.11n operations up to
144 Mbps for 20 MHz and 300 Mbps for 40 MHz
respectively, and 802.11a/b/g data rates.
Additional features include Maximal Likelihood
(ML) decoding, Low-Density Parity Check
(LDPC), Maximal Ratio Combining (MRC), Tx
Beamforming (TxBF), and On-Chip One-Time
Programmable (OTP) memory.
The AR9344 PCIE Root Complex interface can be
used to connect to another Atheros single-chip
MAC/BB/radio for dual concurrent WLAN
applications. The AR9344 supports booting from
either NOR or NAND flash. If NOR flash is used
as boot codestore, an additional NAND flash
device can still be connected, for end-user multi-
media storage and other applications.
When connecting the AR9344 to an external host
through the PCIE Endpoint interface, or the USB
Device interface, the AR9344 can off load the host
CPU from computation- intensive functions,
allowing it to focus on its dedicated tasks.
AR9344 System Block Diagram
Features
74Kc MIPS processor with 64 KB I-Cache and
32 KB D-Cache, operating at up to 533 MHz
External 16- or 32-bit DDR1, DDR2 operating
at up to 200 MHz (400 M transfers/sec), or 16-
bit SDRAM memory interface operating at up
to 200 MHz
NAND and SPI NOR Flash memory support
10/100 Ethernet Switch with five IEEE 802.3
Ethernet LAN ports
MII/RMII/RGMII interface
802.3az Energy Efficient Ethernet compliant
Hardware-based NAT & ACL accelerators for
Ethernet interface
Both PCI Express 1.1 Root Complex and
Endpoint interfaces supported
simultaneously
One USB 2.0 controller with built-in MAC/
PHY supports Host or Device mode
Boot from external CPU via PCIE, USB, xMII,
eliminating need for external flash
I2S/SPDIF-out audio interface
SLIC for VOIP/PCM
One low-speed UART (115 Kbps), one high-
speed UART (3 Mbps), and multiple GPIO
pins for general purpose I/O
Fully integrated RF Front-End including PAs
and LNAs
Optional external LNA/PA
25 MHz or 40 MHz reference clock input
1.2 V switching regulator
Advanced power management with dynamic
clock switching for ultra-low power modes
409-pin BGA package
© 2010 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Align®, Atheros XR®, Driving the Wireless Future®, Intellon®, Ethos®, IQUE®,
No New Wires®, Orion®, PLC4Trucks®, Powerpacket®, Spread Spectrum Carrier®, SSC®, ROCm®, Super A/G®, Super G®, Super N®, The Air is Cleaner at 5-GHz®, Total
802.11®, U-Nav®, Wake on Wireless®, Wireless Future. Unleashed Now.®, and XSPAN®, are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain
Technology™, Install N Go™, ROCm™, amp™, Simpli-Fi™, There is Here™, U-Map™, U-Tag™, and 5-UP™ are trademarks of Atheros Communications, Inc. The Atheros
logo is a registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.
COMPANY CONFIDENTIAL
1




AR9344 pdf, 반도체, 판매, 대치품
PRELIMINARY
3.7 ACL .......................................................... 70
3.7.1 ACL Data Structure .................... 70
3.7.2 Global Rules ................................ 72
3.7.3 Entry Programming ................... 73
3.7.4 ACL Programming and Software
Flow .............................................. 73
3.8 Ethernet Switch ...................................... 75
3.9 Five-Port Ethernet Switch ..................... 75
3.9.1 Overview ...................................... 75
3.9.2 Basic Switch Operation .............. 76
3.9.3 Media Access Controllers (MAC)
76
3.9.4 ACL ............................................... 76
3.9.5 Register Access ............................ 77
3.9.6 LED Control ................................. 77
3.9.7 VLANs .......................................... 78
3.9.8 IEEE Port Security ...................... 78
3.9.9 Mirroring ..................................... 78
3.9.10 Broadcast/Multicast/Unknown
Unicast .......................................... 78
3.9.11 IGMP/MLD Snooping ............... 78
3.9.12 Spanning Tree ............................. 79
3.9.13 MIB/Statistics Counters ............ 79
3.9.14 Atheros Header Configuration . 81
3.9.15 IEEE 802.3 Reserved Group
Addresses Filtering Control ...... 81
3.9.16 PPPoE Header Removal ............ 82
4 Audio Interface ............................ 83
4.1 Overview ................................................. 83
4.2 Audio PLL ............................................... 83
4.3 I2S Interface ............................................. 84
4.3.1 External DAC .............................. 84
4.3.2 Sample Sizes and Rates .............. 84
4.3.3 Stereo Software Interface ........... 84
4.4 SPDIF INTERFACE ............................... 84
4.5 Mailbox (DMA Controller) ................... 85
4.5.1 Mailboxes ..................................... 85
4.5.2 MBOX DMA Operation ............. 85
4.5.3 Software Flow Control ............... 86
4.5.4 Mailbox Error Conditions .......... 86
4.5.5 MBOX-Specific Interrupts ......... 86
5 WLAN Medium Access Control
(MAC) 87
5.1 Overview ................................................. 87
5.2 Descriptor ............................................... 87
5.3 Descriptor Format .................................. 88
5.4 Queue Control Unit (QCU) ................ 106
5.5 DCF Control Unit (DCU) .................... 106
5.5.1 DCU State Information ............ 107
5.6 Protocol Control Unit (PCU) .............. 107
6 Digital PHY Block .....................109
6.1 Overview ............................................... 109
6.2 802.11n (MIMO) Mode ........................ 109
6.2.1 Transmitter (Tx) ........................ 109
6.2.2 Receiver (Rx) ............................. 110
6.3 802.11a/b/g Legacy Mode ................. 110
6.3.1 Transmitter ................................ 110
6.3.2 Receiver ...................................... 110
7 Radio Block .................................111
7.1 Receiver (Rx) Block .............................. 112
7.2 Transmitter (Tx) Block ........................ 113
7.3 Synthesizer (SYNTH) Block ............... 114
7.4 Bias/Control (BIAS) Block ................. 114
8 Register Descriptions ................115
8.1 DDR Registers ...................................... 116
8.1.1 DRR DRAM Configuration
(DDR_CONFIG) ....................... 117
8.1.2 DDR DRAM Configuration 2
(DDR_CONFIG2) ..................... 117
8.1.3 DDR Mode Value
(DDR_MODE_REGISTER) ...... 117
8.1.4 DDR Extended Mode
(DDR_EXTENDED_MODE_REGIS
TER) ............................................ 118
8.1.5 DDR Control (DDR_CONTROL) .
118
8.1.6 DDR Refresh Control and
Configuration (DDR_REFRESH) .
118
8.1.7 DDR Read Data Capture Bit Mask
(DDR_RD_DATA_THIS_CYCLE)
118
8.1.8 DQS Delay Tap Control for Byte 0
(TAP_CONTROL_0) ................ 119
8.1.9 DQS Delay Tap Control for Byte 1
(TAP_CONTROL_1) ................ 119
4 • AR9344 Highly-Integrated 802.11n 2x2 2.4/5 GHz Premium SoC
4 December 2010
Atheros Communications, Inc.
COMPANY CONFIDENTIAL

4페이지










AR9344 전자부품, 판매, 대치품
8.7.4 Egress CPU Related DW0
Information
(EG_CPU_REQUESTED_INFO_D
W0) .............................................. 159
8.7.5 Egress DW0 Key (EG_KEY_DW0 )
159
8.7.6 Egress DW1 Key (EG_KEY_DW1)
159
8.7.7 Egress Ageout DW0 Key
(EG_AGER_KEY_DW0) ........... 159
8.7.8 Egress Ageout DW1 Key
(EG_AGER_KEY_DW1) ........... 160
8.7.9 Egress Ager FIFO Signals
(EG_AGER_INFO) .................... 160
8.7.10 Egress Memory (EG_MEM) .... 160
8.7.11 Egress Memory DW0
(EG_MEM_DW0) ...................... 160
8.7.12 Egress Memory DW1
(EG_MEM_DW1) ...................... 161
8.7.13 Egress Memory DW2
(EG_MEM_DW2) ...................... 161
8.7.14 Egress Link List (EG_LINKLIST) .
161
8.7.15 Egress Sub-Table Data
(EG_SUBTABLE) ...................... 161
8.7.16 Egress Timer Ager Values
(EG_AGER_TICK) .................... 162
8.7.17 Egress Ager Timeout
(EG_AGER_TIMEOUT) ........... 162
8.7.18 Ingress CPU Requested LUT Entry
Lookup (IG_CPU_REQ) ........... 162
8.7.19 Ingress CPU Request Status
(IG_CPU_REQ_STATUS) ........ 163
8.7.20 Ingress DW0 Information
(IG_INFO_DW0) ....................... 163
8.7.21 Ingress DW1 Information
(IG_INFO_DW1) ....................... 163
8.7.22 Ingress DW2 Information
(IG_INFO_DW2) ....................... 164
8.7.23 Ingress DW3 Information
(IG_INFO_DW3) ....................... 164
8.7.24 Ingress CPU Related DW0
Information
(IG_CPU_REQUESTED_INFO_DW
0) .................................................. 164
8.7.25 Ingress CPU Related DW1
Information
(IG_CPU_REQUESTED_INFO_DW
PRELIMINARY
1) ................................................. 164
8.7.26 Ingress CPU Related DW2
Information
(IG_CPU_REQUESTED_INFO_DW
2) ................................................. 164
8.7.27 Ingress CPU Related DW3
Information
(IG_CPU_REQUESTED_INFO_DW
3) ................................................. 165
8.7.28 Ingress DW0 Key (IG_KEY_DW0)
165
8.7.29 Ingress Ageout DW0 Key
(IG_AGER_KEY_DW0) ........... 165
8.7.30 Ingress Ager FIFO Signals
(IG_AGER_INFO) .................... 165
8.7.31 Ingress Memory (IG_MEM) .... 166
8.7.32 Ingress Memory DW0
(IG_MEM_DW0) ....................... 166
8.7.33 Ingress Memory DW1
(IG_MEM_DW1) ....................... 166
8.7.34 Ingress Memory DW2
(IG_MEM_DW2) ....................... 166
8.7.35 Ingress Memory DW3
(IG_MEM_DW3) ....................... 166
8.7.36 Ingress Link List (IG_LINKLIST) .
167
8.7.37 Ingress Sub-Table Data
(IG_SUBTABLE) ....................... 167
8.7.38 Ingress Timer Ager Values
(IG_AGER_TICK) ..................... 167
8.7.39 Ingress Ager Timeout
(IG_AGER_TIMEOUT) ............ 167
8.7.40 Tx QoS Arbiter Configuration
(TxQOS_ARB_CFG) ................. 168
8.7.41 Tx Status and Packet Count
(DMATXSTATUS) .................... 168
8.7.42 Local MAC Address Dword0
(LCL_MAC_ADDR_DW0) ...... 168
8.7.43 Local MAC Address Dword1
(LCL_MAC_ADDR_DW1) ...... 169
8.7.44 Next Hop Router’s MAC Address
Dword0
(NXT_HOP_DST_ADDR_DW0) ..
169
8.7.45 Next Hop Router’s MAC Address
Dword1
(NXT_HOP_DST_ADDR_DW1) ..
169
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR9344 Highly-Integrated 802.11n 2x2 2.4/5 GHz Premium SoC • 7
December 2010 7

7페이지



구       성총 70 페이지
다운로드[ AR9344.PDF 데이터시트 ]
구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

전력 반도체 판매 ( IGBT, TR 모듈, SCR, 다이오드 모듈 )

상호 : 아이지 인터내셔날

사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ]



링크공유

링크 :

관련 데이터시트

부품번호상세설명 및 기능제조사
AR9341

Router Solutions

Teslacomm
Teslacomm
AR9344

Highly-Integrated and Feature-Rich IEEE 802.11n 2x2 2.4/5 GHz Premium SoC

Atheros
Atheros

DataSheet.kr    |   2020   |  연락처   |  링크모음   |   검색  |   사이트맵