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AX24C256A 데이터시트 PDF




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부품번호 AX24C256A 기능
기능 128K/256K-bit 2-WIRE SERIAL CMOS EEPROM
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AX24C256A 데이터시트, 핀배열, 회로
AX24C128A/256A
128K/256K-bit 2- WIRE SERIAL CMOS EEPROM
General Description
Features
The AX24C128A/AX24C256A provides
131,072/262,144 bits of serial electrically erasable
and programmable read-only memory (EEPROM)
organized as16,384/32,768 words of 8 bits each.
The device is optimized for use in many industrial
and commercial applications where low-power and
low-voltage operation are essential. The
AX24C128A/AX24C256A is available in space-
saving SOP-8 and TSSOP-8 packages and is
accessed via a two-wire serial interface. In addition,
the AX24C128A/AX24C256A is available in 1.7V
(1.7V to 5.5V) version.
Wide Voltage Operation
- VCC = 1.7V to 5.5V
Operating Ambient Temperature:
-40°C to +85°C
Internally Organized:
- AX24C128A, 16,384 X 8 (128K bits)
- AX24C256A, 32,768 X 8 (256K bits)
Two-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise
Suppression
Bidirectional Data Transfer Protocol
1MHz (5V), 400 KHz (1.7V, 2.5V, 2.7V)
Compatibility
Write Protect Pin for Hardware Data Protection
64-byte Page (128K, 256K) Write Modes
Partial Page Writes Allowed
Self-timed Write Cycle (5 ms max)
High-reliability
- Endurance: 1 Million Write Cycles
- Data Retention: 100 Years
SOP-8 and TSSOP-8 packages
Pin Configuration
SOP-8
TSSOP-8
Pin Configuration
Pin Name
A0 - A2
SDA
SCL
WP
GND
VCC
Type
I
I/O & Open-drain
I
I
P
P
Functions
Address Inputs
Serial Data
Serial Clock Input
Write Protect
Ground
Power Supply
1/14
Axelite Confidential Materials, do not copy or distribute without written consent.
Rev.1.3 Mar.28 2012




AX24C256A pdf, 반도체, 판매, 대치품
AX24C128A/256A
Memory Organization
AX24C128A, 128K SERIAL EEPROM: Internally organized with 256 pages of 64 bytes each, the 128K
requires an 14-bit data word address for random word addressing.
AX24C256A, 256K SERIAL EEPROM: Internally organized with 512 pages of 64 bytes each, the 256K
requires an 15-bit data word address for random word addressing.
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the
SDA pin may change only during SCL low time periods (see to Figure1). Data changes during SCL high
periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede
any other command (see to Figure 2).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence,
the stop command will place the EEPROM in a standby power mode (see Figure 2).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit
words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during the
ninth clock cycle.
STANDBY MODE: The AX24C128A/AX24C256A features a low-power standby mode which is enabled:
(a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations
MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset
by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
4/14
Axelite Confidential Materials, do not copy or distribute without written consent.
Rev.1.3 Mar.28 2012

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AX24C256A 전자부품, 판매, 대치품
AX24C128A/256A
Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit
in the device address word is set to "1". There are three read operations: current address read, random
address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed
during the last read or write operation, incremented by one. This address stays valid between operations as
long as the chip power is maintained. The address "roll over" during read is from the last byte of the last
memory page to the first byte of the first page. The address "roll over" during write is from the last byte of the
current page to the first byte of the same page.
Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the
EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an
input "0" but does generate a following stop condition (see Figure 7).
RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address.
Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the
microcontroller must generate another start condition. The microcontroller now initiates a current address read
by sending a device address with the read/write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond with a "0" but does
generate a following stop condition (see Figure 8).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address
read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the
EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out
sequential data words. When the memory address limit is reached, the data word address will "roll over" and
the sequential read will continue. The sequential read operation is terminated when the microcontroller does
not respond with a "0" but does generate a following stop condition (see Figure 9).
7/14
Axelite Confidential Materials, do not copy or distribute without written consent.
Rev.1.3 Mar.28 2012

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AX24C256A

128K/256K-bit 2-WIRE SERIAL CMOS EEPROM

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