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PDF AD7441 Data sheet ( Hoja de datos )
| Número de pieza | AD7441 | |
| Descripción | 10-/12-Bit ADCs | |
| Fabricantes | Analog Devices | |
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Pseudo Differential Input, 1 MSPS,
10-/12-Bit ADCs in an 8-Lead SOT-23
AD7441/AD7451
FEATURES
Fast throughput rate: 1 MSPS
Specified for VDD of 2.7 V to 5.25 V
Low power at maximum throughput rate:
4 mW maximum at 1 MSPS with VDD = 3 V
9.25 mW maximum at 1 MSPS with VDD = 5 V
Pseudo differential analog input
Wide input bandwidth:
70 dB SINAD at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface:
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Power-down mode: 1 μA maximum
8-lead SOT-23 and MSOP packages
APPLICATIONS
Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation
GENERAL DESCRIPTION
The AD7441/AD74511 are, respectively, 10-/12-bit high speed,
low power, single-supply, successive approximation (SAR),
analog-to-digital converters (ADCs) that feature a pseudo
differential analog input. These parts operate from a single
2.7 V to 5.25 V power supply and achieve very low power
dissipation at high throughput rates of up to 1 MSPS.
The AD7441/AD7451 contain a low noise, wide bandwidth,
differential track-and-hold (T/H) amplifier that handles input
frequencies up to 3.5 MHz. The reference voltage for these
devices is applied externally to the VREF pin and can range from
100 mV to VDD, depending on the power supply and what suits
the application.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the device to interface
with microprocessors or DSPs. The input signals are sampled
on the falling edge of CS when the conversion is initiated.
The SAR architecture of these parts ensures that there are no
pipeline delays.
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN+
VIN–
VREF
12-BIT
T/H
SUCCESSIVE
APPROXIMATION
ADC
AD7441/AD7451 CONTROL LOGIC
SCLK
SDATA
CS
GND
Figure 1.
PRODUCT HIGHLIGHTS
1. Operation with 2.7 V to 5.25 V Power Supplies.
2. High Throughput with Low Power Consumption.
With a 3 V supply, the AD7441/AD7451 offer 4 mW maxi-
mum power consumption for a 1 MSPS throughput rate.
3. Pseudo Differential Analog Input.
4. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock,
allowing the power to be reduced as the conversion time
is reduced through the serial clock speed increase. These
parts also feature a shutdown mode to maximize power
efficiency at lower throughput rates.
5. Variable Voltage Reference Input.
6. No Pipeline Delays.
7. Accurate Control of Sampling Instant via CS Input and
Once-Off Conversion Control.
8. ENOB > 10 Bits Typically with 500 mV Reference.
1 Protected by U.S. Patent Number 6,681,332.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2010 Analog Devices, Inc. All rights reserved.
1 page  
AD7441/AD7451
Parameter
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time1
Throughput Rate
POWER REQUIREMENTS
VDD
IDD6, 7
Normal Mode (Static)
Normal Mode (Operational)
Full Power-Down Mode
Power Dissipation
Normal Mode (Operational)
Full Power-Down
Test Conditions/Comments
A Version
888 ns with an 18 MHz SCLK
Sine wave input
Full-scale step input
16
250
290
1
2.7/5.25
SCLK on or off
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
SCLK on or off
0.5
1.95
1.45
1
VDD = 5 V; 1.55 mW typical for 100 ksps6
VDD = 3 V; 0.6 mW typical for 100 ksps6
VDD = 5 V; SCLK on or off
VDD = 3 V; SCLK on or off
9.25
4
5
3
B Version
16
250
290
1
2.7/5.25
0.5
1.95
1.45
1
9.25
4
5
3
Unit
SCLK cycles
ns max
ns max
MSPS max
V min/max
mA typ
mA max
mA max
μA max
mW max
mW max
μW max
μW max
1 See Terminology section.
2 Analog inputs with slew rates exceeding 27 V/μs (full-scale input sine wave > 3.5 MHz) within the acquisition time can cause the converter to return an incorrect result.
3 A small dc input is applied to VIN– to provide a pseudo ground for VIN+.
4 The AD7451 is functional with a reference input in the range of 100 mV to VDD.
5 Guaranteed by characterization.
6 See the Power vs. Throughput Rate section.
7 Measured with a full-scale dc input.
Rev. D | Page 4 of 24
5 Page 
AD7441/AD7451
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, fS = 1 MSPS, fSCLK = 18 MHz, VDD = 2.7 V to 5.25 V, VREF = 2.5 V, unless otherwise noted.
75
VDD = 5.25V
70 VDD = 4.75V
VDD = 3.6V
65
VDD = 2.7V
60
55
10
100
FREQUENCY (kHz)
1000
Figure 7. SINAD vs. Analog Input Frequency for the AD7451 for
Various Supply Voltages
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1024
2048
CODE
3072
4096
Figure 10. Typical DNL for the AD7451 for VDD = 5 V
0
100mV p-p SINE WAVE ON VDD
NO DECOUPLING ON VDD
–20
–40
–60
VDD = 3V
–80 VDD = 5V
–100
–120
0
100 200 300 400 500 600 700 800 900 1000
SUPPLY RIPPLE FREQUENCY (kHz)
Figure 8. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
0 8192 POINT FFT
fSAMPLE = 1MSPS
–20 fIN = 100kSPS
SINAD = 71dB
THD = –82dB
–40 SFDR = –83dB
–60
–80
–100
–120
–140
0
100 200 300 400
FREQUENCY (kHz)
500
Figure 9. AD7451 Dynamic Performance for VDD = 5 V
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1024
2048
CODE
3072
Figure 11. Typical INL for the AD7451 for VDD = 5 V
4096
10000
9000
9949
CODES
8000
7000
6000
5000
4000
3000
2000
1000
0
2046
27 CODES
24 CODES
2047
2048
2049
CODES
2050
2051
Figure 12. Histogram of 10,000 Conversions of a DC Input for the AD7451
Rev. D | Page 10 of 24
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet AD7441.PDF ] | |
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