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AD7452 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD7452은 전자 산업 및 응용 분야에서
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부품번호 AD7452 기능
기능 12-Bit ADC
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AD7452 데이터시트, 핀배열, 회로
FEATURES
Specified for VDD of 3 V and 5 V
Low power at max throughput rate:
3.3 mW max at 555 kSPS with 3 V supplies
7.25 mW max at 555 kSPS with 5 V supplies
Fully differential analog input
Wide input bandwidth:
70 dB SINAD at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface:
SPI®/QSPI™/MICROWIRE™/DSP compatible
Power-down mode: 1 µA max
8-lead SOT-23 package
APPLICATIONS
Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation
Motor control
GENERAL DESCRIPTION
The AD74521 is a 12-bit, high speed, low power, successive
approximation (SAR) analog-to-digital converter that features a
fully differential analog input. This part operates from a single
3 V or 5 V power supply and features throughput rates up to
555 kSPS.
The part contains a low noise, wide bandwidth, differential
track-and-hold amplifier (T/H) that can handle input
frequencies up to 3.5 MHz. The reference voltage is applied
externally to the VREF pin and can be varied from 100 mV to
3.5 V depending on the power supply and what suits the
application. The value of the reference voltage determines the
common-mode voltage range of the part. With this truly
differential input structure and variable reference input, the
user can select a variety of input ranges and bias points.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the device to interface
with microprocessors or DSPs. The input signals are sampled on
the falling edge of CS, and the conversion is also initiated at this
point.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Differential Input, 555 kSPS
12-Bit ADC in an 8-Lead SOT-23
AD7452
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN+
VIN–
VREF
12-BIT
T/H SUCCESSIVE
APPROXIMATION
ADC
AD7452
CONTROL LOGIC
SCLK
SDATA
CS
GND
Figure 1.
The SAR architecture of this part ensures that there are no
pipeline delays.
The AD7452 uses advanced design techniques to achieve very
low power dissipation.
PRODUCT HIGHLIGHTS
1. Operation with Either 3 V or 5 V Power Supplies.
2. High Throughput with Low Power Consumption. With a
3 V supply, the AD7452 offers 3.3 mW max power
consumption for 555 kSPS throughput.
3. Fully Differential Analog Input.
4. Flexible Power/Serial Clock Speed Management. The
conversion rate is determined by the serial clock, allowing
the power to be reduced as the conversion time is reduced
through the serial clock speed increase. This part also
features a shutdown mode to maximize power efficiency at
lower throughput rates.
5. Variable Voltage Reference Input.
6. No Pipeline Delay.
7. Accurate Control of the Sampling Instant via a CS Input
and Once-Off Conversion Control.
8. ENOB > 8 Bits Typically with 100 mV Reference.
1 Protected by U.S. Patent Number 6,681,332.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.




AD7452 pdf, 반도체, 판매, 대치품
AD7452
AD7452–SPECIFICATIONS
VDD = 2.7 V to 3.6 V, fSCLK = 10 MHz, fS = 555 kSPS, VREF = 2.0 V; VDD = 4.75 V to 5.25 V, fSCLK = 10 MHz, fS = 555 kSPS, VREF = 2.5 V;
VCM1 = VREF; TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) (SINAD)3
Total Harmonic Distortion (THD)3
Peak Harmonic or Spurious Noise3
Intermodulation Distortion (IMD)3
Second-Order Terms
Third-Order Terms
Aperture Delay3
Aperture Jitter3
Full Power Bandwidth3, 4
DC ACCURACY
Resolution
Integral Nonlinearity (INL) 3
Differential Nonlinearity (DNL) 3
Zero-Code Error3
Positive Gain Error3
Negative Gain Error3
ANALOG INPUT
Full-Scale Input Span
Absolute Input Voltage
VIN+
VIN–
DC Leakage Current
Input Capacitance
REFERENCE INPUT
VREF Input Voltage
DC Leakage Current
VREF Input Capacitance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN 8
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance8
Output Coding
Test Conditions/Comments
fIN = 100 kHz
VDD = 4.75 V to 5.25 V, –86 dB typ
VDD = 2.7 V to 3.6 V, –84 dB typ
VDD = 4.75 V to 5.25 V, –86 dB typ
VDD = 2.7 V to 3.6 V, –84 dB typ
fa = 90 kHz, fb = 110 kHz
@ –3 dB
@ –0.1 dB
Guaranteed no missed codes to 12 bits
2 × VREF 5
VCM = VREF
VCM = VREF
When in track/hold
VDD = 4.75 V to 5.25 V (±1% tolerance for
specified performance)
VDD = 2.7 V to 3.6 V (±1% tolerance for
specified performance)
When in track/hold
Typically 10 nA, VIN = 0 V or VDD
VDD = 4.75 V to 5.25 V, ISOURCE = 200 µA
VDD = 2.7 V to 3.6 V, ISOURCE = 200 µA
ISINK = 200 µA
B Version2
70
–76
–74
–76
–74
–89
–89
5
50
20
2.5
12
±1
± 0.95
±6
±2
±2
VIN+ – VIN–
VCM1 ± VREF/2
VCM1 ± VREF/2
±1
30/10
2.56
2.07
±1
10/30
2.4
0.8
±1
10
2.8
2.4
0.4
±1
10
Twos Complement
Unit
dB min
dB max
dB max
dB max
dB max
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
V
V
V
µA max
pF typ
V
V
µA max
pF typ
V min
V max
µA max
pF max
V min
V min
V max
µA max
pF max
Rev. B | Page 3 of 28

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AD7452 전자부품, 판매, 대치품
AD7452
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND
VIN+ to GND
VIN– to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
VREF to GND
Input Current to Any Pin Except Supplies1
Operating Temperature Range
Commercial (B Version)
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 secs)
Infrared (15 secs)
ESD
Rating
–0.3 V to +7 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
–0.3 V to +7 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
±10 mA
–40°C to +85°C
–65°C to +150°C
150°C
211.5°C/W
91.99°C/W
215°C
220°C
1 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1 Transient currents of up to 100 mA will not cause SCR latch-up.
1.6mA IOL
TO OUTPUT
PIN CL
25pF
200µA IOH
1.6V
Figure 3. Load Circuit for Digital Output Timing Specifications
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 6 of 28

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