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PDF MIC5164YMM Data sheet ( Hoja de datos )
| Número de pieza | MIC5164YMM | |
| Descripción | Dual Regulator Controller | |
| Fabricantes | Micrel Semiconductor | |
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MIC5164
Dual Regulator Controller for DDR3
GDDR3/4/5 Memory and High-Speed
Bus Termination
General Description
Features
The MIC5164 is a dual regulator controller designed for
high speed bus termination. It offers a simple, low-cost
JEDEC-compliant solution for terminating high-speed, low-
voltage digital buses (i.e. DDR, DDR2, DDR3, SCSI, GTL,
SSTL, HSTL, LV-TTL, Rambus, LV-PECL, LV-ECL, etc)
with a Power Good (PG) signal.
The MIC5164 controls two external N-Channel MOSFETs
to form two separate regulators. It operates by switching
between either the high-side MOSFET or the low-side
MOSFET depending on whether the current is being
sourced to the load or sunk by the regulator.
Designed to provide a universal solution for bus
termination regardless of input voltage, output voltage, or
load current, the desired MIC5164 output voltage can be
programmed by forcing the reference voltage externally to
the desired voltage.
The MIC5164 operates from an input of 1.35V to 6V, with
a second bias supply input required for operation. It is
available in the tiny MSOP-10 package with an operating
junction temperature range of −40°C to +125°C.
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
• Input voltage range: 1.35V to 6V
• Up to 7A VTT Current
• Tracking programmable output
• Power Good (PG) signal
• Wide bandwidth
• Logic controlled enable input
• Requires minimal external components
• DDR, DDR2, DDR3, memory termination
• −40°C < TJ < +125°C
• JEDEC-compliant bus termination for SCSI, GTL, SSTL,
HSTL, LV-TTL, Rambus, LV-PECL, LV-ECL, etc
• Tiny MSOP-10 package
Applications
• Desktop computers
• Notebook computers
• Communication systems
• Video cards
• DDR/DDR2/DDR3 memory termination
____________________________________________________________________________________________________________
Typical Application
Typical SSTL-2 Application
(Two MOSFETs Support a 3.5A Application)
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
June 2010
M9999-061510
1 page  
Micrel, Inc.
Test Circuit
MIC5164
Figure 1. Test Circuit
June 2010
5 M9999-061510
5 Page 
Micrel, Inc.
Power dissipation in an SSTL circuit will be identical for
both the high-side and low-side MOSFETs. Since the
supply voltage is divided by half to supply VTT, both
MOSFETs have the same voltage dropped across them.
They are also required to be able to sink and source the
same amount of current (for either all 0’s or all 1’s). This
equates to each side being able to dissipate the same
amount of power. Power dissipation calculation for the
high-side driver is as follows:
PD = (VDDQ − VTT) × I_SOURCE
where I_SOURCE is the average source current. Power
dissipation for the low-side MOSFET is as follows:
PD = VTT × I_SINK
where I_SINK is the average sink current.
In a typical 3A peak SSTL_2 circuit, power
considerations for MOSFET selection would occur as
follows:
PD = (VDDQ −VTT) × I_SOURCE
PD = (2.5V −1.25V) × 1.6A
PD = 2W
This typical SSTL_2 application would require the high-
side and low-side N-Channel MOSFETs to be able to
handle 2 Watts each. In higher current applications,
multiple N-Channel MOSFETs may be placed in parallel
to spread the power dissipation. These MOSFETs will
share current, distributing power dissipation across each
device.
The maximum MOSFET die (junction) temperature limits
maximum power dissipation. The ability of the device to
dissipate heat away from the junction is specified by the
junction-to-ambient (θJA) thermal resistance.
This is the sum of junction-to-case (θJC) thermal
resistance, case-to-sink (θCS) thermal resistance and
sink-to-ambient (θSA) thermal resistance:
θJA = θJC + θCS + θSA
MIC5164
In our example of a 3A peak SSTL_2 termination circuit,
we have selected a D-pack N-Channel MOSFET that
has a maximum junction temperature of 125°C. The
device has a junction-to-case thermal resistance of
1.5°C/Watt. Our application has a maximum ambient
temperature of 60°C. The required junction-to-ambient
thermal resistance can be calculated as follows:
θ JA
=
TJ − TA
PD
Where TJ is the maximum junction temperature, TA is the
maximum ambient temperature and PD is the power
dissipation.
In our example:
θ JA
=
TJ − TA
PD
θJA
=
125°C - 60°C
2W
θJA = 32.5°C / W
This shows that our total thermal resistance must be
better than 32.5°C/W. Since the total thermal resistance
is a combination of all the individual thermal resistances,
the amount of heat sink required can be calculated as
follows:
θSA = θJA − (θJC + θCS)
In our example:
θSA = 32.5°C / W - (1.5°C / W + 0.5°C / W )
θ SA = 30 .5 °C / W
In most cases, case-to-sink thermal resistance can be
assumed to be about 0.5°C/W.
The SSTL termination circuit for our example, using two
D-pack N-Channel MOSFETs (one high-side and one
low-side) will require enough copper area to spread the
heat from the MOSFET. In this example to dissipate 2W
from TO-252 package a 2 oz copper of 1.0 in2 on
component side is required. In some cases, airflow may
also help to reduce thermal resistance. For different
MOSFET package refer to manufacturer Data Sheet for
copper area requirements.
June 2010
11 M9999-061510
11 Page | ||
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