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Micrel Semiconductor에서 제조한 전자 부품 MIC5162은 전자 산업 및 응용 분야에서
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부품번호 MIC5162 기능
기능 Dual Regulator Controller
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MIC5162 데이터시트, 핀배열, 회로
MIC5162
Dual Regulator Controller for DDR3
GDDR3/4/5 Memory and High-Speed
Bus Termination
General Description
Features
The MIC5162 is a dual regulator controller designed for
high speed bus termination. It offers a simple, low-cost
JEDEC compliant solution for terminating high-speed, low-
voltage digital buses (i.e. DDR, DDR2, DDR3, SCSI, GTL,
SSTL, HSTL, LV-TTL, Rambus, LV-PECL, LV-ECL, etc).
The MIC5162 controls two external N-Channel MOSFETs
to form two separate regulators. It operates by switching
between either the high-side MOSFET or the low-side
MOSFET depending upon whether the current is being
sourced to the load or sunk by the regulator.
Designed to provide a universal solution for bus
termination regardless of input voltage, output voltage, or
load current. The desired MIC5162 output voltage can be
programmed by forcing the reference voltage externally to
desired voltage.
The MIC5162 operates from an input of 1.35V to 6V, with
a second bias supply input required for operation. It is
available in a tiny MSOP-10 package with operating
junction temperature range of -40°C to +125°C.
Input voltage range: 1.35V to 6V
Up to 7A VTT Current
Tracking programmable output
Wide bandwidth
Logic controlled enable input
Requires minimal external components
DDR, DDR2, DDR3, memory termination
-40°C < TJ < +125°C
JEDEC Compliant Bus Termination for SCSI, GTL,
SSTL, HSTL, LV-TTL, Rambus, LV-PECL, LV-ECL, etc
Tiny MSOP-10 package
Applications
Desktop Computers
Notebook computers
Communication systems
Data sheets and support documentation can be found on Video cards
Micrel’s web site at: www.micrel.com.
DDR/DDR2/DDR3 memory termination
____________________________________________________________________________________________________________
Typical Application
Typical SSTL-2 Application
(Two MOSFETs Support a 3.5A Application)
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
March 2010
M9999-033110




MIC5162 pdf, 반도체, 판매, 대치품
Micrel, Inc.
Test Circuit
MIC5162
March 2010
4 M9999-033110

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MIC5162 전자부품, 판매, 대치품
Micrel, Inc.
Application Information
High performance memory requires high speed
signaling. This means special attention must be paid to
maintain signal integrity. Bus termination provides a
means to increase signaling speed while maintaining
good signal integrity. An example of bus termination is
the Series Stub Termination Logic or SSTL. Figure 1 is
an example of an SSTL 2 single ended series parallel
terminated output. SSTL 2 is a JEDEC signaling
standard operating off a 2.5V supply. It consists of a
series resistor (RS) and a terminating resistor (RT).
Values of RS range between 10Ω to 30Ω with a typical of
22Ω, while RT ranges from 22Ω to 28Ω with a typical
value of 25Ω. VREF must maintain 1/2 VDD with a ±1%
tolerance, while VTT will dynamically sink and source
current to maintain a termination voltage of ±40mV from
the VREF line under all conditions. This method of bus
termination reduces common mode noise, settling time,
voltage swings, EMI/RFI and improves slew rates.
The MIC5162 is a high performance linear controller,
utilizing scalable N-Channel MOSFETs to provide
JEDEC-compliant bus termination. Termination is
achieved by dividing down the VDDQ voltage by half,
providing the reference (VREF) voltage. An internal error
amplifier compares the termination voltage (VTT) and
VREF, controlling 2 external N-Channel MOSFETs to sink
and source current to maintain a termination voltage
(VTT) equal to VREF. The N-Channels receive their
enhancement voltage from a separate VCC pin on the
device.
Although this document focuses mostly on SSTL, the
MIC5162 is also capable of providing bus terminations
for SCSI, GTL, HSTL, LV-TTL, Rambus, LV-PECL,
DDR, DDR2, DDR3 memory termination and other
systems.
MIC5162
VDDQ
The VDDQ pin on the MIC5162 provides the source
current through the high-side N-Channel and the
reference voltage to the device. The MIC5162 can
operate at VDDQ voltages as low as 1.35V. Due to the
possibility of large transient currents being sourced from
this line, significant bypass capacitance will aid in
performance by improving the source impedance at
higher frequencies. Since the reference is simply VDDQ/2,
perturbations on the VDDQ will also appear at half the
amplitude on the reference. For this reason, low ESR
capacitors such as ceramics or OS-CON are
recommended on VDDQ.
VTT
VTT is the actual termination point. VTT is regulated to
VREF. Due to high speed signaling, the load current seen
by VTT is constantly changing. To maintain adequate
large signal transient response, large OS-CON and
ceramics are recommended on VTT. The proper
combination and placement of the OS-CON and ceramic
capacitors is important to reduce both ESR and ESL
such that high-current and high-speed transients do not
exceed the dynamic voltage tolerance requirement of
VTT. The larger OS-CON capacitors provide bulk charge
storage while the smaller ceramic capacitors provide
current during the fast edges of the bus transition. Using
several smaller ceramic capacitors distributed near the
termination resistors is typically important to reduce the
effects of PCB trace inductance.
VREF
Two resistors dividing down the VDDQ voltage provide
VREF (Figure 3). The resistors are valued at around
17kΩ. A minimum capacitor value of 120pF from VREF to
ground is required to remove high frequency signals
reflected from the source. Large capacitance values
(>1500pF) should be avoided. Values greater than
1500pF slow down VREF and detract from the reference
voltage’s ability to track VDDQ during high speed load
transients.
Figure 1. SSTL-2 Termination
March 2010
Figure 2. MIC5162 as a DDR Memory Termination
for 3.5A Application
7 M9999-033110

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