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PDF MIC5165YMM Data sheet ( Hoja de datos )
| Número de pieza | MIC5165YMM | |
| Descripción | Dual Regulator Controller | |
| Fabricantes | Micrel Semiconductor | |
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MIC5165
Dual Regulator Controller for DDR3
GDDR3/4/5 Memory Termination
General Description
Features
The MIC5165 is a dual regulator controller designed
specifically for low-voltage memory termination
applications such as DDR3 and GDDR3/4/5. The MIC5165
offers a simple, low-cost JEDEC-compliant solution for
terminating high-speed, low-voltage digital buses with a
Power Good (PG) signal.
The MIC5165 controls two external N-Channel MOSFETs
to form two separate regulators. It operates by switching
between either the high-side MOSFET or the low-side
MOSFET, depending on whether the current is being
sourced to the load or being sunk by the regulator.
Designed to provide a universal solution for memory
termination regardless of input voltage, output voltage, or
load current, the desired MIC5165 output voltage can be
programmed by forcing the reference voltage externally to
the desired voltage.
The MIC5165 operates from an input voltage as low as
0.75V up to 6V, with a second bias supply input required
for operation. The MIC5165 is available in a tiny MSOP-10
package with an operating junction temperature range of
–40°C to +125°C.
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
• Input voltage range: 0.75V to 6V
• Up to 7A VTT Current
• Tracking programmable output
• Power Good signal
• Wide bandwidth
• Logic-controlled enable input
• Requires minimal external components
• DDR3, GDDR3/4/5 memory termination
• -40°C < TJ < +125°C
• Tiny MSOP-10 package
Applications
• Desktop Computers
• Servers
• Notebook computers
• Workstations
• DDR3 andGDDR3/4/5 Memory Termination
____________________________________________________________________________________________________________
Typical Application
MIC5165 as a DDR3 Memory Termination Device for 3.5A Application
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
June 2010
M9999-061510-B
1 page  
Micrel, Inc.
Test Circuit
MIC5165
Figure 1. Test Circuit
June 2010
5 M9999-061510-B
5 Page 
Micrel, Inc.
Application Information
Synchronous Dynamic Random Access Memory
(SDRAM) has continually evolved over the years to keep
up with ever-increasing computing needs. The latest
addition to SDRAM technology is DDR3 SDRAM. DDR3
SDRAM is the third generation of the DDR SDRAM
family and offers improved power savings, higher data
bandwidth and enhanced signal quality with multiple On-
Die Termination (ODT) selection. In DDR3 SDRAM the
values of the ODT are based on the value of an external
resistor. In addition to using this external resistor for
setting the ODT value, it is also used for calibrating the
ODT value so that it maintains its resistance value to
within a 10% tolerance.
To improve signal integrity and support higher frequency
operation of memory read/write, the JEDEC committee
defined a fly-by termination scheme used with the
clocks, the command bus and address bus signals. The
fly-by topology reduces Simultaneous Switching Noise
(SSN) by deliberately causing flight-time skew between
the data and strobes at every DRAM as the clock,
address and command signals traverse the DIMM.
The DDR3 SDRAM uses a programmable impedance
output buffer. Currently, there are two drive strength
settings, 34Ω and 40Ω. The 40Ω drive strength setting is
currently a reserved specification defined by JEDEC, but
available on the DDR3 SDRAM.
Figure 3. Dynamic OCT between Stratix III/IV
FPGA Devices
MIC5165
The MIC5165 provides two drive signals, the high-side
MOSFET acts as a pass element to provide output
voltage and low side MOSFET acts as pull-down to
regulate the output termination voltage (VTT). An internal
error amplifier compares the termination voltage (VTT)
and VREF, controlling two external N-Channel MOSFETs
to sink or source current to maintain a termination
voltage (VTT) equal to VREF. These MOSFETs receive
their enhancement voltage from a separate VCC pin on
the device. Although the general discussion is focused
on DDR3, the MIC5165 is also capable of providing bus
terminations for DDR, DDR2 and GDDR3/4/5.
VDDQ
The MIC5165 can operate at VDDQ voltages as low as
0.75V. Due to the possibility of large transient currents
being sourced from this line, significant bypass
capacitance will increase performance by improving the
source impedance at higher frequencies. Since the
reference is simply VDDQ/2, perturbations on VDDQ will
also appear at half the amplitude on the reference. For
this reason, low-ESR capacitors such as ceramics or
OS-CON are recommended on VDDQ.
VTT
The proper combination and placement of the OS-CON
and ceramic capacitors is important to reduce both ESR
and ESL such that high-current high-speed transients do
not exceed the dynamic voltage tolerance requirement of
VTT. The OS-CON capacitors provide bulk charge
storage while the smaller ceramic capacitors provide
current during the fast edges of the bus transition. Using
several smaller ceramic capacitors distributed near the
termination resistors is typically important to reduce the
effects of PCB trace inductance.
VREF
A minimum capacitor value of 120pF from VREF to
ground is required to remove high-frequency signals
reflected from the source (Refer to Figure 4). Large
capacitance values (>1500pF) should be avoided.
Values greater than 1500pF slow down VREF and detract
from the reference voltage’s ability to track VDDQ during
high speed load transients.
June 2010
Figure 4. MIC5165 as a DDR3 Memory Termination Device
for 7A Application
11 M9999-061510-B
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