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PDF MIC5167 Data sheet ( Hoja de datos )
| Número de pieza | MIC5167 | |
| Descripción | Synchronous Buck DDR Memory Terminator | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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MIC5167
1MHz, 6A, Integrated Switch,
High-Efficiency, Synchronous Buck
DDR Memory Terminator
General Description
Features
The MIC5167 is a high-efficiency, 6A, integrated switch,
synchronous regulator designed for use as a double data
rate (DDR) or quad data rate (QDR) terminator. The
MIC5167 is optimized for highest efficiency, achieving
more than 94% efficiency while still switching at 1MHz
over a broad range. The device works with a small 0.4µH
inductor and 300µF output capacitor. The MIC5167 offers
a simple, low-cost, JEDEC-compliant solution for
terminating high-speed, low-voltage, digital buses (i.e.
DDR, DDR2, DDR3, DDR3L, DDR3UL, DDR4, SCSI, GTL,
SSTL, HSTL, LV-TTL, LV-PECL, and LV_ECL) with a
Power-Good (PG) output.
The output voltage is controlled externally by input to the
VDDQ pin. The output voltage is one-half the voltage
applied to the VDDQ pin. The output voltage can be
adjusted down to 0.6V to address low-voltage power
needs. The MIC5167 will source 6A and sink up to 6A.
A window comparator monitors the output voltage and
controls the PG output. If the output voltage is outside
±15% limit of VREF the PG is driven low.
The MIC5167 is available in a 24-pin 4mm x 4mm MLF®
with a junction operating range from –40°C to +125°C.
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
• Input voltage range: 2.6V to 5.5V
• VTT voltage adjustable down to 0.35V
• Output load current up to ±6A
• Power-Good (PG) fault flag
• Efficiency > 94% across a broad load range
• Ultra-fast transient response
• Easy RC compensation
• 100% maximum duty cycle
• Fully-integrated MOSFET switches
• Micropower shutdown
• Thermal-shutdown and current-limit protection
• 24-pin 4mm x 4mm MLF®
• –40°C to +125°C junction temperature range
Applications
• Double data rate (DDR) or quad data rate (QDR)
memory terminator
• High power density point-of-load conversion
• Servers and routers
• DVD recorders / Blu-ray players
• Computing peripherals
• Base stations
• FPGAs, DSP, and low-voltage ASIC power
____________________________________________________________________________________________________________
Typical Application
MIC5167 ±6A Synchronous Buck DDR Terminator
Ramp Control is a trademark of Micrel, Inc.
MLF and MicroLeadFrame are registered trademarks of Amkor Technology, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
January 2012
M9999-012312-B
1 page  
Micrel, Inc.
MIC5167
Electrical Characteristics(4) (Continued)
SVIN = PVIN = VEN/DLY = 3.3V, VFB = VTT = 0.6V, TA = 25°C, unless noted. Bold values indicate –40°C< TJ < +125°C.
Parameter
Condition
Min. Typ.
Power-Good (PG)
PG Window
Hysteresis
Threshold % of VTT from VREF
±10 ±15
2.5
PG Output Low Voltage
IPG = 5mA (sinking), VFB = 0.4V; VEN = VIN
130
PG Leakage Current
VPG = 5.5V; VFB = 0.625V
Thermal Protection
Over-Temperature Shutdown
Over-Temperature Shutdown
Hysteresis
TJ Rising
160
20
Max.
±20
1.0
2.0
Notes:
1. Exceeding the absolute maximum rating may damage the device.
2. Devices are ESD sensitive. Handling precautions recommended.
3. The device is not guaranteed to function outside its operating rating.
4. Specification for packaged product only.
Units
%
%
mV
μA
°C
°C
January 2012
5 M9999-012312-B
5 Page 
Micrel, Inc.
Application Information
DDR memory requires two power supplies, one for the
memory chip, referred to as VDDQ and the other for a
termination supply VTT, which is one-half VDDQ. With
memory speeds in excess of 300MHz, the memory
system bus must be treated as transmission lines. To
maintain good signal integrity the memory bus must be
terminated to minimize signal reflections. Figure 2 shows
the simplified termination circuit. Each control, address
and data lines have these termination resistors RS and
RT connected to them.
VDDQ
1.8V
VIN
5.0V
22µF
x4
VDDQ
CHIP SET
VDDQ
+
RS
RT
VDDQ
DDR
MEMORY
-
+
RS
RT
VREF
-
+
MIC5167
VDDQ
PVIN
SVIN
PGND
FB
SW
EP
SGND
VREF
0.4µH
100pF
VTT/0.9V
100µF
x3
Figure 2. DDR Memory Termination Circuit
Bus termination provides a means to increase signaling
speed while maintaining good signal integrity. The
termination network consists of a series resistor (RS)
and a terminating resistor (RT). Values of RS range
between 10Ω to 30Ω with a typical of 22Ω, while RT
ranges from 22Ω to 28Ω with a typical value of 25Ω. VTT
will dynamically sink and source current to maintain a
termination voltage under all conditions. This method of
bus termination reduces common mode noise, settling
time, voltage swings, EMI/RFI and improves slew rates.
VDDQ powers all the memory IC’s, memory drivers and
receivers for all the memory bits in the DDR memory
system. When the driver is logic low VTT sources current.
When the driver is logic high VTT sinks current. The
MIC5167 regulates VTT to VDDQ/2 during sourcing or
sinking current. The power dissipated in RS (bus
resistance) and RT (termination resistance) is VTT
squared divided by their respective resistance.
MIC5167
Since the voltage across the resistance is VDDQ/2, the
power dissipated is one-quarter the power of a
termination voltage of VDDQ. The memory bits are not
usually all at a logic high or logic low at the same time so
the VTT supply is usually not sinking or sourcing much
current.
VTT
VTT is regulated to VREF. Due to high speed signaling, the
load current seen by VTT is constantly changing. To
maintain adequate transient response, large OS-CON
and ceramics are recommended on VTT. The proper
combination and placement of the OS-CON and ceramic
capacitors is important to reduce both ESR and ESL
such that high-current and high-speed transients do not
exceed the dynamic voltage tolerance requirement of
VTT. The larger OS-CON capacitors provide bulk charge
storage while the smaller ceramic capacitors provide
current during the fast edges of the bus transition. Using
several smaller ceramic capacitors distributed near the
termination resistors is important to reduce the effects of
PCB trace inductance.
When VTT is sinking current, the external power supply
that powers the MIC5167 (PVIN) must be able to sink
current-to-ground; otherwise, the supply voltage will start
to increase. It is crucial that this external power supply
must also be able to source and sink current.
VDDQ
The VDDQ input on the MIC5167 is used to create the
internal reference voltage for VTT. The reference voltage
is generated from an internal resistor divider network of
two 60kΩ resistors, generating a reference voltage VREF
that is VDDQ/2. The VDDQ input should be Kelvin
connected as close as possible to the memory supply
voltage.
Since the reference is simply VDDQ/2, any perturbations
on VDDQ will also appear at half the amplitude on the
reference. For this reason, both ceramics and low-ESR
bulk capacitors such as OS-CON are recommended on
the VDDQ supply. This will aid in performance by
improving the source impedance over a wide frequency
range.
Feedback
The feedback (FB) pin provides the path for the error
amplifier to regulate VTT. The FB input must also be
Kelvin connected to the VTT bypass capacitors. If the FB
input is connected to close to the MIC5167, the IR drop
of the PCB trace can cause the VTT voltage at the
memory chip to be too low. Placing the MIC5167 as
close as possible to the DDR memory will improve the
load regulation performance.
January 2012
11 M9999-012312-B
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet MIC5167.PDF ] | |
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