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PDF AD5694R Data sheet ( Hoja de datos )
| Número de pieza | AD5694R | |
| Descripción | Quad 16-/14-/12-Bit nanoDAC+ | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Quad 16-/14-/12-Bit nanoDAC+
with 2 ppm/°C Reference, I2C Interface
AD5696R/AD5695R/AD5694R
FEATURES
High relative accuracy (INL): ±2 LSB maximum @ 16 bits
Low drift 2.5 V reference: 2 ppm/°C typical
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
Total unadjusted error (TUE): ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
Low glitch: 0.5 nV-sec
400 kHz I2C-compatible serial interface
Robust 3.5 kV HBM and 1.5 kV FICDM ESD rating
Low power: 3.3 mW at 3 V
2.7 V to 5.5 V power supply
−40°C to +105°C temperature range
APPLICATIONS
Optical transceivers
Base-station power amplifiers
Process control (PLC I/O cards)
Industrial automation
Data acquisition systems
GENERAL DESCRIPTION
The AD5696R/AD5695R/AD5694R family, are low power,
quad, 16-/14-/12-bit buffered voltage output DACs. The devices
include a 2.5 V, 2 ppm/°C internal reference (enabled by
default) and a gain select pin giving a full-scale output of 2.5 V
(gain = 1) or 5 V (gain = 2). All devices operate from a single
2.7 V to 5.5 V supply, are guaranteed monotonic by design, and
exhibit less than 0.1% FSR gain error and 1.5 mV offset error
performance. The devices are available in a 3 mm × 3 mm
LFCSP and a TSSOP package.
The AD5696R/AD5695R/AD5694R also incorporate a power-
on reset circuit and a RSTSEL pin that ensures that the DAC
outputs power up to zero scale or midscale and remain there
until a valid write takes place. Each part contains a per-channel
power-down feature that reduces the current consumption of
the device to 4 µA at 3 V while in power-down mode.
The AD5696R/AD5695R/AD5694R use a versatile 2-wire serial
interface that operates at clock rates up to 400 kHz, and
includes a VLOGIC pin intended for 1.8 V/3 V/5 V logic.
FUNCTIONAL BLOCK DIAGRAM
VDD
GND
VREF
VLOGIC
SCL
SDA
A1
A0
AD5696R/AD5695R/AD5694R
2.5V
REFERENCE
INPUT
REGISTER
DAC
STRING
REGISTER DAC A
INPUT
REGISTER
DAC
STRING
REGISTER DAC B
INPUT
REGISTER
DAC
STRING
REGISTER DAC C
INPUT
REGISTER
DAC
STRING
REGISTER DAC D
POWER-ON
RESET
GAIN =
×1/×2
BUFFER
VOUTA
BUFFER
VOUTB
BUFFER
VOUTC
BUFFER
POWER-
DOWN
LOGIC
VOUTD
LDAC RESET
RSTSEL
Figure 1.
GAIN
Table 1. Quad nanoDAC+ Devices
Interface Reference 16-Bit
SPI Internal AD5686R
External AD5686
I2C Internal AD5696R
External AD5696
14-Bit
AD5685R
AD5695R
12-Bit
AD5684R
AD5684
AD5694R
AD5694
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL).
AD5696R (16-bit): ±2 LSB maximum
AD5695R (14-bit): ±1 LSB maximum
AD5694R (12-bit): ±1 LSB maximum
2. Low Drift 2.5 V On-Chip Reference.
2 ppm/°C typical temperature coefficient
5 ppm/°C maximum temperature coefficient
3. Two Package Options.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD5696R/AD5695R/AD5694R
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise
noted.1
Table 3.
Parameter2
Min Typ Max Unit
Output Voltage Settling Time
AD5696R
5 8 µs
AD5695R
5 8 µs
AD5694R
5 7 µs
Slew Rate
0.8 V/µs
Digital-to-Analog Glitch Impulse
0.5
nV-sec
Digital Feedthrough
0.13 nV-sec
Digital Crosstalk
0.1 nV-sec
Analog Crosstalk
0.2 nV-sec
DAC-to-DAC Crosstalk
0.3 nV-sec
Total Harmonic Distortion4
−80 dB
Output Noise Spectral Density
300
nV/√Hz
Output Noise
6 µV p-p
SNR 90 dB
SFDR
83 dB
SINAD
80 dB
Test Conditions/Comments3
¼ to ¾ scale settling to ±2 LSB
¼ to ¾ scale settling to ±2 LSB
¼ to ¾ scale settling to ±2 LSB
1 LSB change around major carry
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
DAC code = midscale, 10 kHz; gain = 2
0.1 Hz to 10 Hz
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
1 Guaranteed by design and characterization; not production tested.
2 See the Terminology section.
3 Temperature range is −40°C to +105°C, typical @ 25°C.
4 Digitally generated sine wave @ 1 kHz.
Rev. B | Page 5 of 32
5 Page 
Data Sheet
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
VDD = 5V
TA = 25°C
–1.0 INTERNAL REFERENCE = 2.5V
0 2500 5000 7500
10000
12500
CODE
Figure 17. AD5695R DNL
15000 16383
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
VDD = 5V
TA = 25°C
–1.0 INTERNAL REFERENCE = 2.5V
0 625 1250 1875
2500
3125
CODE
Figure 18. AD5694R DNL
3750 4096
10
8
6
4
2 INL
0
DNL
–2
–4
–6
–8
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–10
–40 10
60
110
TEMPERATURE (°C)
Figure 19. INL Error and DNL Error vs. Temperature
AD5696R/AD5695R/AD5694R
10
8
6
4
2
INL
0
DNL
–2
–4
–6
–8
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–10
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VREF (V)
Figure 20. INL Error and DNL Error vs. VREF
10
8
6
4
2
INL
0
DNL
–2
–4
–6
–8
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–10
2.7 3.2 3.7 4.2 4.7 5.2
SUPPLY VOLTAGE (V)
Figure 21. INL Error and DNL Error vs. Supply Voltage
0.10
0.08
0.06
0.04
0.02 FULL-SCALE ERROR
0
–0.02
GAIN ERROR
–0.04
–0.06
–0.08
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–0.10
–40 –20 0
20 40 60 80 100 120
TEMPERATURE (°C)
Figure 22. Gain Error and Full-Scale Error vs. Temperature
Rev. B | Page 11 of 32
11 Page | ||
| Páginas | Total 32 Páginas | |
| PDF Descargar | [ Datasheet AD5694R.PDF ] | |
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