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Número de pieza | SPE0522S52RG | |
Descripción | 2-Line ESD Protection Array | |
Fabricantes | SYNC POWER | |
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Hay una vista previa y un enlace de descarga de SPE0522S52RG (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
No Preview Available ! SPE0522
2-Line ESD Protection Array
DESCRIPTION
The SPE0522 are designed by TVS bi-direction device that
is to protect sensitive electronics from damage or latch-up
due to ESD. They are designed for use in applications
where board space is at a premium. SPE0522 will protect
up to two lines, and may be used on lines where the signal
polarities swing above and below ground.
SPE0522 offer desirable characteristics for board level
protection including fast response time, low operating and
clamping voltage, and no device degradation.
SPE0522 may be used to meet the immunity requirements
of IEC 61000-4-2, level 4. The small SOT-523 package
makes them ideal for use in portable electronics such as
cell phones, PDA’s, notebook computers, and digital
cameras.
APPLICATIONS
Cellular Handsets and Accessories
Cordless Phone
PDA
Notebooks and Handhelds
Portable Instrumentation
Digital Cameras
MP3 Player
FEATURES
Transient protection for data lines to
IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
Protects two I/O lines
Working voltage: 5V
Low leakage current
Low operating and clamping voltages
PIN CONFIGURATION ( SOT-523 / SC-89 )
PART MARKING
2011/08/01 Ver.5
Page 1
1 page SPE0522
2-Line ESD Protection Array
APPLICATION NOTE
Device Connection for Protection of Two Data Lines
SPE0522 is designed to protect up to two data lines. The bidirection device is connected as follows:
1. The TVS protection of two I/O lines is achieved by connecting pins 1 and 2 to the data lines. Pin 3 is connected
to ground. The ground connection should be made directly to the ground plane for best results. The path length
is kept as short as possible to reduce the effects of parasitic inductance.
Circuit Board Layout Recommendations for Suppression of ESD
Good circuit board layout is critical for the suppression of ESD induced transients. The following guidelines are
recommended:
1. Place the TVS near the input terminals or connectors to restrict transient coupling.
2. Minimize the path length between the TVS and the protected line.
3. Minimize all conductive loops including power and ground loops.
4. The ESD transient return path to ground should be kept as short as possible.
5. Never run critical signals near board edges.
6. Use ground planes whenever possible.
2011/08/01 Ver.5
Page 5
5 Page |
Páginas | Total 7 Páginas | |
PDF Descargar | [ Datasheet SPE0522S52RG.PDF ] |
Número de pieza | Descripción | Fabricantes |
SPE0522S52RG | 2-Line ESD Protection Array | SYNC POWER |
SPE0522S52RGB | 2-Line ESD Protection Array | SYNC POWER |
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