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PDF SPE1244 Data sheet ( Hoja de datos )
| Número de pieza | SPE1244 | |
| Descripción | 3-Line ESD Protection Array | |
| Fabricantes | SYNC POWER | |
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SPE1244
3-Line ESD Protection Array
DESCRIPTION
The SPE1244 are designed by TVS array that is to protect
sensitive electronics from damage or latch-up due to ESD.
They are designed for use in applications where board
space is at a premium. SPE1244 will protect up to three
line, and may be used on lines where the signal polarities
swing above and below ground.
SPE1244 offer desirable characteristics for board level
protection including fast response time, low operating and
clamping voltage, and no device degradation.
SPE1244 may be used to meet the immunity requirements
of IEC 61000-4-2, level 4. The small SOT-143 package
makes them ideal for use in portable electronics such as
cell phones, PDA’s, notebook computers, and digital
cameras.
APPLICATIONS
ADSL
Industrial Electronics
RS-422 Interfaces
Portable Electronics
Microcontroller Input Protection
WAN/LAN Equipment
FEATURES
Transient protection for data lines to
IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
Protects four I/O lines
Working voltage: 12V
Low leakage current
Low operating and clamping voltages
PIN CONFIGURATION ( SOT-143-A )
PART MARKING ( SOT-143-A )
2009/12/30 Ver.1
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1 page  
SPE1244
3-Line ESD Protection Array
APPLICATION NOTE
Device Connection for Protection of Four Data Lines
SPE1244 is designed to protect up to three data lines. The device is connected as follows:
1. The TVS protection of four I/O lines is achieved by connecting pins 1, 2, 4. Pin 3 are connected to ground. The
ground connection should be made directly to the ground plane for best results. The path length is kept as short
as possible to reduce the effects of parasitic inductance.
Circuit Board Layout Recommendations for Suppression of ESD
Good circuit board layout is critical for the suppression of ESD induced transients. The following guidelines are
recommended:
1. Place the TVS near the input terminals or connectors to restrict transient coupling.
2. Minimize the path length between the TVS and the protected line.
3. Minimize all conductive loops including power and ground loops.
4. The ESD transient return path to ground should be kept as short as possible.
5. Never run critical signals near board edges.
6. Use ground planes whenever possible.
2009/12/30 Ver.1
Page 5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet SPE1244.PDF ] | |
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